Rohan makes RTL on FPGA 🛠️
@rohan-devarc.bsky.social
Exploring the ASIC lore.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
Pinned
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
October 28, 2025 at 5:10 AM
This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
October 26, 2025 at 2:50 PM
This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
October 16, 2025 at 8:36 PM
Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
Reposted by Rohan makes RTL on FPGA 🛠️
Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about
@wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs
@wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs
Teardown Session 56: wafer.space with Tim Ansell
YouTube video by Crowd Supply
youtu.be
September 30, 2025 at 6:00 AM
Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about
@wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs
@wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs
FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda.
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
September 28, 2025 at 10:44 AM
FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda.
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
Reposted by Rohan makes RTL on FPGA 🛠️
It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!
What happens when one of the main providers that enables #opensource #silicon to thrive...shuts down? Companies like @mith.ro's new wafer.space jump in and offer an even more compelling option. $7K for 1000 chips on the GlobalFoundries GF180MCU process. Learn more:
theamphour.com/703-building...
theamphour.com/703-building...
September 25, 2025 at 9:23 PM
It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
September 6, 2025 at 8:18 AM
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
SPI-slave device for seven-segment display on TT base board.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
August 10, 2025 at 12:12 PM
SPI-slave device for seven-segment display on TT base board.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
ASICs are cool.
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
August 5, 2025 at 4:24 PM
ASICs are cool.
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
Definitely true!
August 4, 2025 at 11:02 PM
Definitely true!
Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
July 28, 2025 at 2:01 PM
Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
When man craves for aesthetics, he craves for God...and good quality probes.
July 27, 2025 at 2:37 PM
When man craves for aesthetics, he craves for God...and good quality probes.
Reposted by Rohan makes RTL on FPGA 🛠️
2025 One Hertz Challenge: A 555, but not as we know it
2025 One Hertz Challenge: A 555, but not as we know it
Hackaday Article
hackaday.com
July 22, 2025 at 8:10 PM
2025 One Hertz Challenge: A 555, but not as we know it
Reposted by Rohan makes RTL on FPGA 🛠️
Join me today on the #opensourcesiliconstream to catch up on the latest news and then make a simple quadrature encoder peripheral for the @tinytapeout.com RISC-V competition!
www.youtube.com/live/2JTFwLV...
www.youtube.com/live/2JTFwLV...
Open Source Silicon Stream #18 - Quadrature Encoder RISC-V peripheral
Join the stream for latest news in open source silicon, followed by some hacking on a quadrature encoder peripheral for the Tiny Tapeout RISC-V competition.
https://docs.google.com/document/d/197sZCd...
www.youtube.com
July 21, 2025 at 11:24 AM
Join me today on the #opensourcesiliconstream to catch up on the latest news and then make a simple quadrature encoder peripheral for the @tinytapeout.com RISC-V competition!
www.youtube.com/live/2JTFwLV...
www.youtube.com/live/2JTFwLV...
It looks good. Got the power led.
Now trying to get it to work as intended.
Now trying to get it to work as intended.
July 21, 2025 at 4:13 PM
It looks good. Got the power led.
Now trying to get it to work as intended.
Now trying to get it to work as intended.
Booted KianV uLinux from Hirosh on TinyTapeout ASIC.
July 18, 2025 at 8:19 PM
Booted KianV uLinux from Hirosh on TinyTapeout ASIC.
I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA.
Had to visit a nearby university to get the X-ray inspection done.
Had to visit a nearby university to get the X-ray inspection done.
July 14, 2025 at 4:05 PM
I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA.
Had to visit a nearby university to get the X-ray inspection done.
Had to visit a nearby university to get the X-ray inspection done.
July 11, 2025 at 1:08 PM
My TT06 board arrived!
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
July 8, 2025 at 6:58 AM
My TT06 board arrived!
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
Must read papers for processor design.
January 12, 2025 at 10:52 AM
Must read papers for processor design.
Reposted by Rohan makes RTL on FPGA 🛠️
I’ve got MicroPython running on TinyQV - my RISC-V SoC that’s on #TinyTapeout 6.
Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.
Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.
January 5, 2025 at 7:24 PM
I’ve got MicroPython running on TinyQV - my RISC-V SoC that’s on #TinyTapeout 6.
Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.
Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.
Reposted by Rohan makes RTL on FPGA 🛠️
I've got my hands on TT06 and I'll be bringing up my Risc-V SoC on #TinyTapeout 6 this evening.
I'll mostly post about it over on Fediverse: rebel-lion.uk/@mike/113765...
I'll mostly post about it over on Fediverse: rebel-lion.uk/@mike/113765...
Mike Bell (@mike@rebel-lion.uk)
Attached: 1 image
Finally got my hands on #TinyTapeout 06! I’ve been really looking forward to this, it has my RISC-V RV32EC SoC, which (assuming it works) should be much faster and more flexible tha...
rebel-lion.uk
January 3, 2025 at 4:34 PM
I've got my hands on TT06 and I'll be bringing up my Risc-V SoC on #TinyTapeout 6 this evening.
I'll mostly post about it over on Fediverse: rebel-lion.uk/@mike/113765...
I'll mostly post about it over on Fediverse: rebel-lion.uk/@mike/113765...
This is a VAAMAN board. This board features an RK3399 MPU, an Efinix T120 FPGA w/ 112k logic elements, and a high-speed CPU-FPGA link.
I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.
I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.
January 6, 2025 at 8:10 PM
This is a VAAMAN board. This board features an RK3399 MPU, an Efinix T120 FPGA w/ 112k logic elements, and a high-speed CPU-FPGA link.
I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.
I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.
Turns out that mech keyboards don't last. Back to the classic membrane keyboard!
January 4, 2025 at 9:36 PM
Turns out that mech keyboards don't last. Back to the classic membrane keyboard!
__cooking xv6-riscv on ecp5__
__Have a nice weekend guys__
__Have a nice weekend guys__
January 3, 2025 at 8:20 PM
__cooking xv6-riscv on ecp5__
__Have a nice weekend guys__
__Have a nice weekend guys__