Rohan makes RTL on FPGA 🛠️
@rohan-devarc.bsky.social
Exploring the ASIC lore.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers.
For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...
For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
October 28, 2025 at 5:12 AM
Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers.
For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...
For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...
Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface.
Metal 1: used for local interconnects, this allowed short and dense wiring.
Metal 2: used for global signals like buses, clocks, power.
Metal 1: used for local interconnects, this allowed short and dense wiring.
Metal 2: used for global signals like buses, clocks, power.
October 28, 2025 at 5:11 AM
Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface.
Metal 1: used for local interconnects, this allowed short and dense wiring.
Metal 2: used for global signals like buses, clocks, power.
Metal 1: used for local interconnects, this allowed short and dense wiring.
Metal 2: used for global signals like buses, clocks, power.
🤩🤩
Another mike bell project to fab!
Another mike bell project to fab!
October 28, 2025 at 5:09 AM
🤩🤩
Another mike bell project to fab!
Another mike bell project to fab!
Fomu fpga?
October 27, 2025 at 4:22 AM
Fomu fpga?
chinese semiconductor industry is creative for sure.
Nice idea for analog tapeout for some day.
Nice idea for analog tapeout for some day.
October 26, 2025 at 2:50 PM
chinese semiconductor industry is creative for sure.
Nice idea for analog tapeout for some day.
Nice idea for analog tapeout for some day.
And guess what whole hdl for this is written in both system verilog and chisel/scala.
October 16, 2025 at 8:38 PM
And guess what whole hdl for this is written in both system verilog and chisel/scala.
Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first.
Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.
Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.
October 16, 2025 at 8:37 PM
Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first.
Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.
Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.
We already have chisel for this right? or it lacks on something that only Haskell can provide?
September 30, 2025 at 6:53 AM
We already have chisel for this right? or it lacks on something that only Haskell can provide?
It can be powered directly from a Pi USB port
with 60% brightness. It needs a external supply for 100% brightness.
with 60% brightness. It needs a external supply for 100% brightness.
September 25, 2025 at 8:26 AM
It can be powered directly from a Pi USB port
with 60% brightness. It needs a external supply for 100% brightness.
with 60% brightness. It needs a external supply for 100% brightness.
it's ROM generated from ROM compiler.
*This is the one for storing TV codes for that IR LED project
*and not the atari one
*This is the one for storing TV codes for that IR LED project
*and not the atari one
September 16, 2025 at 11:50 AM
it's ROM generated from ROM compiler.
*This is the one for storing TV codes for that IR LED project
*and not the atari one
*This is the one for storing TV codes for that IR LED project
*and not the atari one
There is one Open Z80 implementation by @renaldas.bsky.social on TT07.
www.tinytapeout.com/chips/tt07/t...
www.tinytapeout.com/chips/tt07/t...
259 Zilog Z80 - Tiny Tapeout
Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
www.tinytapeout.com
September 11, 2025 at 4:39 AM
There is one Open Z80 implementation by @renaldas.bsky.social on TT07.
www.tinytapeout.com/chips/tt07/t...
www.tinytapeout.com/chips/tt07/t...
yeah, openroad STA gives you a rough estimate for power.
It's a static power estimation obviously. Also it's a digital tapeout, so I don't expect it to be a very power hungry design (assuming SKY130A cells are optimized).
It's a static power estimation obviously. Also it's a digital tapeout, so I don't expect it to be a very power hungry design (assuming SKY130A cells are optimized).
September 6, 2025 at 2:55 PM
yeah, openroad STA gives you a rough estimate for power.
It's a static power estimation obviously. Also it's a digital tapeout, so I don't expect it to be a very power hungry design (assuming SKY130A cells are optimized).
It's a static power estimation obviously. Also it's a digital tapeout, so I don't expect it to be a very power hungry design (assuming SKY130A cells are optimized).
or get a TT board and learn fpga and design asic as well.
bsky.app/profile/roha...
bsky.app/profile/roha...
SPI-slave device for seven-segment display on TT base board.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
August 14, 2025 at 5:53 PM
or get a TT board and learn fpga and design asic as well.
bsky.app/profile/roha...
bsky.app/profile/roha...
LMAO
Come for India and you'll get a bloody nose.
Come for India and you'll get a bloody nose.
August 7, 2025 at 8:47 AM
LMAO
Come for India and you'll get a bloody nose.
Come for India and you'll get a bloody nose.
The clock looks so beautiful because it's right from FPGA!!
August 5, 2025 at 4:33 PM
The clock looks so beautiful because it's right from FPGA!!