Rohan makes RTL on FPGA 🛠️
@rohan-devarc.bsky.social
Exploring the ASIC lore.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
Not your typical lobste. rs link-dumper or book-cover–posting zombie.
This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
October 28, 2025 at 5:10 AM
This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
chinese semiconductor industry is creative for sure.
Nice idea for analog tapeout for some day.
Nice idea for analog tapeout for some day.
October 26, 2025 at 2:50 PM
chinese semiconductor industry is creative for sure.
Nice idea for analog tapeout for some day.
Nice idea for analog tapeout for some day.
This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
October 26, 2025 at 2:50 PM
This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.
So this is actually a analog matrix.
Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
October 16, 2025 at 8:36 PM
Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda.
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
September 28, 2025 at 10:44 AM
FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda.
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
September 6, 2025 at 8:18 AM
Low power math within few clock cycles.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
Imagine it, then put it into silicon.
Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.
Check - t.co/vBGGA2i0uX
Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
SPI-slave device for seven-segment display on TT base board.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
August 10, 2025 at 12:12 PM
SPI-slave device for seven-segment display on TT base board.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
LMAO
Come for India and you'll get a bloody nose.
Come for India and you'll get a bloody nose.
August 7, 2025 at 8:47 AM
LMAO
Come for India and you'll get a bloody nose.
Come for India and you'll get a bloody nose.
The clock looks so beautiful because it's right from FPGA!!
August 5, 2025 at 4:33 PM
The clock looks so beautiful because it's right from FPGA!!
ASICs are cool.
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
August 5, 2025 at 4:24 PM
ASICs are cool.
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
FPGAs are ❤️.
FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social
@tinytapeout.com @mattvenn.net @urishaked.bsky.social
Definitely true!
August 4, 2025 at 11:02 PM
Definitely true!
Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
July 28, 2025 at 2:01 PM
Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
...and beautiful waveforms
July 27, 2025 at 3:27 PM
...and beautiful waveforms
When man craves for aesthetics, he craves for God...and good quality probes.
July 27, 2025 at 2:37 PM
When man craves for aesthetics, he craves for God...and good quality probes.
FYI CONFIG_PROGRAMN pin is high, since configuration never really began. When I do ecp_prog.execute() It goes low for a fraction of sec then high back again.
And after uploading blinky, I should observe 2.5v on TP5, right ?
bsky.app/profile/roha...
And after uploading blinky, I should observe 2.5v on TP5, right ?
bsky.app/profile/roha...
July 22, 2025 at 8:21 AM
FYI CONFIG_PROGRAMN pin is high, since configuration never really began. When I do ecp_prog.execute() It goes low for a fraction of sec then high back again.
And after uploading blinky, I should observe 2.5v on TP5, right ?
bsky.app/profile/roha...
And after uploading blinky, I should observe 2.5v on TP5, right ?
bsky.app/profile/roha...
FPGA brother to @tinytapeout.com ASIC.
July 21, 2025 at 4:21 PM
FPGA brother to @tinytapeout.com ASIC.
It looks good. Got the power led.
Now trying to get it to work as intended.
Now trying to get it to work as intended.
July 21, 2025 at 4:13 PM
It looks good. Got the power led.
Now trying to get it to work as intended.
Now trying to get it to work as intended.
I'm getting this
It is not able to read ECP5 ID, now what? ( there is power LED on fpga though)
It is not able to read ECP5 ID, now what? ( there is power LED on fpga though)
July 21, 2025 at 2:18 PM
I'm getting this
It is not able to read ECP5 ID, now what? ( there is power LED on fpga though)
It is not able to read ECP5 ID, now what? ( there is power LED on fpga though)
Booted KianV uLinux from Hirosh on TinyTapeout ASIC.
July 18, 2025 at 8:19 PM
Booted KianV uLinux from Hirosh on TinyTapeout ASIC.
Then there is also qspi pmod by Mike and Leo Moser, which I also fabricated.
July 14, 2025 at 4:17 PM
Then there is also qspi pmod by Mike and Leo Moser, which I also fabricated.
I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA.
Had to visit a nearby university to get the X-ray inspection done.
Had to visit a nearby university to get the X-ray inspection done.
July 14, 2025 at 4:05 PM
I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA.
Had to visit a nearby university to get the X-ray inspection done.
Had to visit a nearby university to get the X-ray inspection done.
this one is little sharp but still not very clear on visuals.
July 11, 2025 at 3:15 PM
this one is little sharp but still not very clear on visuals.
July 11, 2025 at 1:08 PM
My TT06 board arrived!
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
July 8, 2025 at 6:58 AM
My TT06 board arrived!
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com @mattvenn.net
Doing same on axon with help from @aksharvastarpara.bsky.social
January 30, 2025 at 5:58 AM
Doing same on axon with help from @aksharvastarpara.bsky.social