Low power math within few clock cycles.

Imagine it, then put it into silicon.

Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.

Check - t.co/vBGGA2i0uX

Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.

SPI-slave device for seven-segment display on TT base board.

TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.

ASICs are cool.
FPGAs are ❤️.

FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social

@tinytapeout.com @mattvenn.net @urishaked.bsky.social

Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.

FYI CONFIG_PROGRAMN pin is high, since configuration never really began. When I do ecp_prog.execute() It goes low for a fraction of sec then high back again.

And after uploading blinky, I should observe 2.5v on TP5, right ?
bsky.app/profile/roha...

Booted KianV uLinux from Hirosh on TinyTapeout ASIC.

this one is little sharp but still not very clear on visuals.

MPW5 up-close and zoomed-in!
@tinytapeout.com @mattvenn.net @urishaked.bsky.social