PipelineC
@pipelinec.bsky.social
PipelineC Hardware Description Language
An easy to understand hardware description language with a powerful autopipelining compiler and growing set of real life design inspired features.
github.com/JulianKemmerer/PipelineC
https://discord.gg/Aupm3DDrK2
An easy to understand hardware description language with a powerful autopipelining compiler and growing set of real life design inspired features.
github.com/JulianKemmerer/PipelineC
https://discord.gg/Aupm3DDrK2
Pinned
PipelineC
@pipelinec.bsky.social
· Nov 17
Sphery vs. Shapes
YouTube video by Victor Suarez Rovere
youtu.be
You Bluesky folks seen this awesome work?
First raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA!
#raytracing #graphics #hardware #gamedev #hdl #verilog #vhdl #eda
youtu.be/hn3sr3VMJQU
First raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA!
#raytracing #graphics #hardware #gamedev #hdl #verilog #vhdl #eda
youtu.be/hn3sr3VMJQU
Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
github.com
January 3, 2026 at 4:09 PM
Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
github.com
January 1, 2026 at 7:56 PM
Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer...
#fpga #rtl #hdl #hls #aoc25
#fpga #rtl #hdl #hls #aoc25
github.com
December 26, 2025 at 7:36 PM
Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄
github.com/JulianKemmer...
#fpga #rtl #hdl #hls #aoc25
github.com/JulianKemmer...
#fpga #rtl #hdl #hls #aoc25
github.com
December 22, 2025 at 3:03 PM
Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz.
~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls
~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls
github.com
December 20, 2025 at 4:40 PM
Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz.
~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls
~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls
"How do FPGAs execute blocking assignments in one clock cycle?"
Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.
www.reddit.com/r/FPGA/comme...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.
www.reddit.com/r/FPGA/comme...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
Software, FPGA Execution, a PipelineC response
www.reddit.com
August 7, 2025 at 9:37 PM
How to send a struct from one dev board to another? A PipelineC Story
#hdl #hls #RTL #fpga #ethernet #i2s #hardware
www.reddit.com/r/FPGA/comme...
#hdl #hls #RTL #fpga #ethernet #i2s #hardware
www.reddit.com/r/FPGA/comme...
From the FPGA community on Reddit: How to send a struct from one dev board to another?
Explore this post and more from the FPGA community
www.reddit.com
July 24, 2025 at 9:24 PM
Reposted by PipelineC
implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA
glasgow-embedded.org/latest/apple...
glasgow-embedded.org/latest/apple...
jtag-xvc - Glasgow Interface ExplorerContentsMenuExpandLight modeDark modeAuto light/dark, in light modeAuto light/dark, in dark mode
glasgow-embedded.org
May 22, 2025 at 5:51 AM
implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA
glasgow-embedded.org/latest/apple...
glasgow-embedded.org/latest/apple...
Reposted by PipelineC
#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing".
insidehpc.com/2025/04/jaso...
C-to-gates was a dream until Cong made it real.
insidehpc.com/2025/04/jaso...
C-to-gates was a dream until Cong made it real.
April 9, 2025 at 3:52 PM
#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing".
insidehpc.com/2025/04/jaso...
C-to-gates was a dream until Cong made it real.
insidehpc.com/2025/04/jaso...
C-to-gates was a dream until Cong made it real.
Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...
March 14, 2025 at 3:19 PM
Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...
What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing!
github.com/JulianKemmer...
github.com/JulianKemmer...
February 20, 2025 at 8:21 PM
#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have.
Just assign to #UART debug probe wire:
github.com/JulianKemmer...
Just assign to #UART debug probe wire:
github.com/JulianKemmer...
February 20, 2025 at 8:13 PM
Reposted by PipelineC
👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible.
Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech!
#introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD
Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech!
#introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD
February 2, 2025 at 7:01 PM
👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible.
Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech!
#introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD
Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech!
#introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD
Reposted by PipelineC
I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits.
Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...
Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...
January 18, 2025 at 6:52 PM
I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits.
Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...
Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...
Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @raspberrypi.com. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
January 10, 2025 at 4:04 PM
Gifted a new #FPGA dev board this season? 🤓 PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls
github.com/JulianKemmer...
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls
github.com/JulianKemmer...
Dev Board Setup
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC
github.com
December 26, 2024 at 4:19 PM
Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA
It’s become a cliche, but hardware is hard! One reason why hardware is harder than software is that the time between revisions is often longer. We need to wait for new PCBs, or for components to be delivered. Or for more new PCBs after we realise we got it wrong!
December 15, 2024 at 5:29 AM
Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA
Reposted by PipelineC
To help others progress, I’m going to award several Christmas test gear grants. If you’re interested, apply here: www.zerotoasiccourse.com/post/test-eq...
Test Equipment Grant
Apply for a grant to spend on test equipment
www.zerotoasiccourse.com
December 14, 2024 at 7:49 PM
To help others progress, I’m going to award several Christmas test gear grants. If you’re interested, apply here: www.zerotoasiccourse.com/post/test-eq...
Reposted by PipelineC
If you like thinking like: computers are the best thing humans have ever invented, ~= ASICs are practically pinnacle of science/innovation etc
then an FPGA on your desk at home
is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓
then an FPGA on your desk at home
is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓
just found out what an fpga is today and they sound like actual magic?? like you can just *program connections between gates like that*?????? actual insanity
December 4, 2024 at 5:21 PM
If you like thinking like: computers are the best thing humans have ever invented, ~= ASICs are practically pinnacle of science/innovation etc
then an FPGA on your desk at home
is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓
then an FPGA on your desk at home
is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓
Have been super pleased with the ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded
pico-ice: Main Page
pico-ice.tinyvision.ai
November 30, 2024 at 7:20 PM
Have been super pleased with the ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded