RascalFoxfire aka. the funky CPU fox
rascalfoxfire.bsky.social
RascalFoxfire aka. the funky CPU fox
@rascalfoxfire.bsky.social
German computer engineering student, professional madman, freetime CPU/GPU designer, hobby OS and compiler dev, 2D and 3D beginner artist and cyborgfox!

Art profile: @rascalfoxfirearts.bsky.social
I packed it full with a lot of new stuff i had to develop over time like the half precision FPU and the MMU. It also comes with 4-stage partial forwarding pipeline, interrupts with different priorities, timer, ring mode, a lot of MMU configurations, separate main memory/IO address space, ...
November 19, 2025 at 12:34 AM
As a german bread enjoyer i can confirm: perfection
November 6, 2025 at 10:35 PM
Btw. the ROB is messy but works quite well. But you can see here why implicit renaming designs weren't much of a thing and why explicit renaming is the name of the games today
November 1, 2025 at 12:13 AM
Okay, a little more spoiling: i am creating an universal compiler which you can feed a simple .json with your ISAs instruction and behaviour and then does the rest without much intervention. That is why i am going this route. But fair, i could at that point prob even use something like LLVM
October 1, 2025 at 10:55 PM
Ah okay, i understood. Well that was the initial idea: start with the current universal assembler and then putting the compiler on top. But i am derivating here since i need a custom IR for some suprise that will help us later. Can't spoil too much rn since it is still all just could/should/hope
September 30, 2025 at 11:26 PM
Ah thank you! Well, i got an assembler running but there is quite a lot more to the story since the compiler will be also a technological demonstrator for something that looks quite promising (for short: universal compiler). But any help is welcome and i will definitely make a deep dive into yours!
September 30, 2025 at 7:15 PM
Thanks for the double reminder...
September 26, 2025 at 9:26 PM