RascalFoxfire aka. the funky CPU fox
@rascalfoxfire.bsky.social
German computer engineering student, professional madman, freetime CPU/GPU designer, hobby OS and compiler dev, 2D and 3D beginner artist and cyborgfox!
Art profile: @rascalfoxfirearts.bsky.social
Art profile: @rascalfoxfirearts.bsky.social
Ladies and gentlemen, SuperSatellit, my 16 bit high performance OS ready CPU based on the same named custom ISA, is done! I still need to do a lot of testing and expanding some parts like the MMU and FPU but all features are in!
November 19, 2025 at 12:31 AM
Ladies and gentlemen, SuperSatellit, my 16 bit high performance OS ready CPU based on the same named custom ISA, is done! I still need to do a lot of testing and expanding some parts like the MMU and FPU but all features are in!
And switched tasks again. Buuuut i am back at the large 16 bit CPU of mine! And now with some great news: i got the half precision FPU running! Still need to implement the edge cases but SuperSatellit can now technically do 3D stuff and more! If someone need it, i can put it on GitHub
November 14, 2025 at 9:39 PM
And switched tasks again. Buuuut i am back at the large 16 bit CPU of mine! And now with some great news: i got the half precision FPU running! Still need to implement the edge cases but SuperSatellit can now technically do 3D stuff and more! If someone need it, i can put it on GitHub
Found out a way for scalable register renaming and dependency solving between pipelines! That is now for my PRF 4-way OoOE CPU version. Free list is also implemented and ready to go. Next will be the actual PRF and the register port scheduler
November 14, 2025 at 2:16 AM
Found out a way for scalable register renaming and dependency solving between pipelines! That is now for my PRF 4-way OoOE CPU version. Free list is also implemented and ready to go. Next will be the actual PRF and the register port scheduler
Not much going on here, just further tinkering on my compiler and the OoOE CPUs. Still alive (at least i think... so am i?)
November 6, 2025 at 1:27 AM
Not much going on here, just further tinkering on my compiler and the OoOE CPUs. Still alive (at least i think... so am i?)
Aaaaaaand i shifted focus again on my magic compiler. Well, at least i should be then able to make something useful for my 16 bit OoOE CPUs. And if i get that running i also have directly a toolchain for my large SuperSatellit 16 bit CPU
November 2, 2025 at 2:23 AM
Aaaaaaand i shifted focus again on my magic compiler. Well, at least i should be then able to make something useful for my 16 bit OoOE CPUs. And if i get that running i also have directly a toolchain for my large SuperSatellit 16 bit CPU
Ladies and gentlemens: my OoOE CPU executed its first instructions and in parallel! Seems like i got all the routing and control issues out. Next will be the memory unit and branches. It is still a POS since it got some inconvenient flaws but i guess that it is still very solid for a first OoOE CPU
November 1, 2025 at 12:11 AM
Ladies and gentlemens: my OoOE CPU executed its first instructions and in parallel! Seems like i got all the routing and control issues out. Next will be the memory unit and branches. It is still a POS since it got some inconvenient flaws but i guess that it is still very solid for a first OoOE CPU
Lesson learned, ROBs in data-in-ROB CPUs are messy. Every entry needs to listen on my 5 CDB lines + the 4 commit stages. Meaning i need 9 x 24 (instructions my ROB can handle) comparators, 24 9-way encoders and MUXes and more stuff. Now i know why we use PRF designs today instead
October 31, 2025 at 1:15 AM
Lesson learned, ROBs in data-in-ROB CPUs are messy. Every entry needs to listen on my 5 CDB lines + the 4 commit stages. Meaning i need 9 x 24 (instructions my ROB can handle) comparators, 24 9-way encoders and MUXes and more stuff. Now i know why we use PRF designs today instead
My brain decided to multitask back to the OoOE 16 bit CPU... well, i managed to build the commit bus to the reservation stations (needed in case a finished value is send to the ROB, a follow up instruction depends on it but the value wasn't yet commited to the register file). Next into the ROB!
October 30, 2025 at 12:26 AM
My brain decided to multitask back to the OoOE 16 bit CPU... well, i managed to build the commit bus to the reservation stations (needed in case a finished value is send to the ROB, a follow up instruction depends on it but the value wasn't yet commited to the register file). Next into the ROB!
Build a little more on the 16 bit RISC CPU. Interrupts should run now (i hope). Gonna test it tomorrow. The compiler is coming along quite nicely but still slow going
October 22, 2025 at 11:53 PM
Build a little more on the 16 bit RISC CPU. Interrupts should run now (i hope). Gonna test it tomorrow. The compiler is coming along quite nicely but still slow going
Finished the config file, onward to the actual compiler. Still deep within the code
October 18, 2025 at 12:40 AM
Finished the config file, onward to the actual compiler. Still deep within the code
Still on the compiler. I nearly finished writing the config file for the Companion CPU. Meanwhile i started implementing a project safe/load feature into the actual compiler
October 17, 2025 at 12:42 AM
Still on the compiler. I nearly finished writing the config file for the Companion CPU. Meanwhile i started implementing a project safe/load feature into the actual compiler
Got a first logisim implementation of CompanionNISC in its most basic BI32 variant! It doesn't even have the register file extensions but that is was the plan. Very simple, still quite powerful. Time to build some software and compare it with a RISC-V 32I!
October 16, 2025 at 12:35 AM
Got a first logisim implementation of CompanionNISC in its most basic BI32 variant! It doesn't even have the register file extensions but that is was the plan. Very simple, still quite powerful. Time to build some software and compare it with a RISC-V 32I!
Not much from my side, still on going easy on programming. Progress is slow since i burned out a little from all the hardware tinkering
October 9, 2025 at 12:01 AM
Not much from my side, still on going easy on programming. Progress is slow since i burned out a little from all the hardware tinkering
Okay, compilerwise i started implementing the first modules to get from my custom IR to the target arch. Currently suprisingly smooth riding
October 4, 2025 at 12:49 AM
Okay, compilerwise i started implementing the first modules to get from my custom IR to the target arch. Currently suprisingly smooth riding
Not ded but quite busy. Currently on my compiler to get finally some test software on my CPUs without going to hexadecimal and/or assembler again
September 30, 2025 at 12:43 AM
Not ded but quite busy. Currently on my compiler to get finally some test software on my CPUs without going to hexadecimal and/or assembler again
Okay, i am half back mentally. Focus shifted back to the Pico-Series of ISAs and subsequent CPUs but now i am back at the 16 bit CPU to finish the interrupt and ring system!
September 22, 2025 at 11:37 PM
Okay, i am half back mentally. Focus shifted back to the Pico-Series of ISAs and subsequent CPUs but now i am back at the 16 bit CPU to finish the interrupt and ring system!
Back from the east with some fresh energy to continue! Time to get back to original business: the large 16 bit CPU with floating point stuff!
September 16, 2025 at 12:36 AM
Back from the east with some fresh energy to continue! Time to get back to original business: the large 16 bit CPU with floating point stuff!
Going offline for the weekend, got into an adventure to an old GDR bunker. But before that i shall share the following wisdome i just learned: implicit renaming is funny on paper but bad in hardware, go explicit on your adventures. Tune in next time!
September 11, 2025 at 9:11 PM
Going offline for the weekend, got into an adventure to an old GDR bunker. But before that i shall share the following wisdome i just learned: implicit renaming is funny on paper but bad in hardware, go explicit on your adventures. Tune in next time!
Tinkered a little on the 4-way implicit renaming CPU variant. The 2-way in order CPU uses the same ISA. I only need the load store unit, the reorder buffer, a smart instruction dispatcher and later the branch prediction system from the in order CPU. Next CPU in that series will use explicit renaming
September 8, 2025 at 12:08 AM
Tinkered a little on the 4-way implicit renaming CPU variant. The 2-way in order CPU uses the same ISA. I only need the load store unit, the reorder buffer, a smart instruction dispatcher and later the branch prediction system from the in order CPU. Next CPU in that series will use explicit renaming
Quite some easy days here. Did a little more on the super scalar CPUs, managed to write a lil on the GPU ISA and even started to implement the interrupts into my large 16 bit CPU
September 5, 2025 at 12:00 AM
Quite some easy days here. Did a little more on the super scalar CPUs, managed to write a lil on the GPU ISA and even started to implement the interrupts into my large 16 bit CPU
Small update: started the FPU edge case detection for my large 16 bit CPU, build a lil on the branch prediction for the in order CPU and managed to start the OoOE 16 bit CPU based on the in order CPU. I guess 4 input instruction pipelines are enough for the OoOE experiment
August 30, 2025 at 12:50 AM
Small update: started the FPU edge case detection for my large 16 bit CPU, build a lil on the branch prediction for the in order CPU and managed to start the OoOE 16 bit CPU based on the in order CPU. I guess 4 input instruction pipelines are enough for the OoOE experiment
YES!!! Ladies and gentlemen, my first functional super scalar CPU! It still lacks the jump/branch and memory operations but i managed to get the first operations run parallely. I also managed to include operand forwarding with cross pipeline forwarding and pipeline swap compensation! What an act...
August 26, 2025 at 1:36 AM
YES!!! Ladies and gentlemen, my first functional super scalar CPU! It still lacks the jump/branch and memory operations but i managed to get the first operations run parallely. I also managed to include operand forwarding with cross pipeline forwarding and pipeline swap compensation! What an act...
Did a lil in the super scalar experimental department with the simple 16 bit ISA. Inspired by the Motorola 68060 i started building it with two pipelines, one supporting the full ISA (A) while the second (B) won't have a Mul/Div and Jump/Branch unit. They can even swap instructions when needed!
August 25, 2025 at 1:21 AM
Did a lil in the super scalar experimental department with the simple 16 bit ISA. Inspired by the Motorola 68060 i started building it with two pipelines, one supporting the full ISA (A) while the second (B) won't have a Mul/Div and Jump/Branch unit. They can even swap instructions when needed!
Did a lil on the FPU today, still an endless fight. Did also quickly design a very simple 16 bit RISC ISA to test some accelerating technologies like in order and out of order superscalarity since my previous attempt went wrong
August 24, 2025 at 12:59 AM
Did a lil on the FPU today, still an endless fight. Did also quickly design a very simple 16 bit RISC ISA to test some accelerating technologies like in order and out of order superscalarity since my previous attempt went wrong
Small update: got the signed short to float16 and vice versa converter of my FPU ready. Next an extension to the MMU and the FPU adder/subtractor
August 19, 2025 at 12:43 AM
Small update: got the signed short to float16 and vice versa converter of my FPU ready. Next an extension to the MMU and the FPU adder/subtractor