RascalFoxfire aka. the funky CPU fox
@rascalfoxfire.bsky.social
German computer engineering student, professional madman, freetime CPU/GPU designer, hobby OS and compiler dev, 2D and 3D beginner artist and cyborgfox!
Art profile: @rascalfoxfirearts.bsky.social
Art profile: @rascalfoxfirearts.bsky.social
Ladies and gentlemen, SuperSatellit, my 16 bit high performance OS ready CPU based on the same named custom ISA, is done! I still need to do a lot of testing and expanding some parts like the MMU and FPU but all features are in!
November 19, 2025 at 12:31 AM
Ladies and gentlemen, SuperSatellit, my 16 bit high performance OS ready CPU based on the same named custom ISA, is done! I still need to do a lot of testing and expanding some parts like the MMU and FPU but all features are in!
And switched tasks again. Buuuut i am back at the large 16 bit CPU of mine! And now with some great news: i got the half precision FPU running! Still need to implement the edge cases but SuperSatellit can now technically do 3D stuff and more! If someone need it, i can put it on GitHub
November 14, 2025 at 9:39 PM
And switched tasks again. Buuuut i am back at the large 16 bit CPU of mine! And now with some great news: i got the half precision FPU running! Still need to implement the edge cases but SuperSatellit can now technically do 3D stuff and more! If someone need it, i can put it on GitHub
Found out a way for scalable register renaming and dependency solving between pipelines! That is now for my PRF 4-way OoOE CPU version. Free list is also implemented and ready to go. Next will be the actual PRF and the register port scheduler
November 14, 2025 at 2:16 AM
Found out a way for scalable register renaming and dependency solving between pipelines! That is now for my PRF 4-way OoOE CPU version. Free list is also implemented and ready to go. Next will be the actual PRF and the register port scheduler
Btw. the ROB is messy but works quite well. But you can see here why implicit renaming designs weren't much of a thing and why explicit renaming is the name of the games today
November 1, 2025 at 12:13 AM
Btw. the ROB is messy but works quite well. But you can see here why implicit renaming designs weren't much of a thing and why explicit renaming is the name of the games today
Ladies and gentlemens: my OoOE CPU executed its first instructions and in parallel! Seems like i got all the routing and control issues out. Next will be the memory unit and branches. It is still a POS since it got some inconvenient flaws but i guess that it is still very solid for a first OoOE CPU
November 1, 2025 at 12:11 AM
Ladies and gentlemens: my OoOE CPU executed its first instructions and in parallel! Seems like i got all the routing and control issues out. Next will be the memory unit and branches. It is still a POS since it got some inconvenient flaws but i guess that it is still very solid for a first OoOE CPU
My brain decided to multitask back to the OoOE 16 bit CPU... well, i managed to build the commit bus to the reservation stations (needed in case a finished value is send to the ROB, a follow up instruction depends on it but the value wasn't yet commited to the register file). Next into the ROB!
October 30, 2025 at 12:26 AM
My brain decided to multitask back to the OoOE 16 bit CPU... well, i managed to build the commit bus to the reservation stations (needed in case a finished value is send to the ROB, a follow up instruction depends on it but the value wasn't yet commited to the register file). Next into the ROB!
Got a first logisim implementation of CompanionNISC in its most basic BI32 variant! It doesn't even have the register file extensions but that is was the plan. Very simple, still quite powerful. Time to build some software and compare it with a RISC-V 32I!
October 16, 2025 at 12:35 AM
Got a first logisim implementation of CompanionNISC in its most basic BI32 variant! It doesn't even have the register file extensions but that is was the plan. Very simple, still quite powerful. Time to build some software and compare it with a RISC-V 32I!
Tinkered a little on the 4-way implicit renaming CPU variant. The 2-way in order CPU uses the same ISA. I only need the load store unit, the reorder buffer, a smart instruction dispatcher and later the branch prediction system from the in order CPU. Next CPU in that series will use explicit renaming
September 8, 2025 at 12:08 AM
Tinkered a little on the 4-way implicit renaming CPU variant. The 2-way in order CPU uses the same ISA. I only need the load store unit, the reorder buffer, a smart instruction dispatcher and later the branch prediction system from the in order CPU. Next CPU in that series will use explicit renaming
YES!!! Ladies and gentlemen, my first functional super scalar CPU! It still lacks the jump/branch and memory operations but i managed to get the first operations run parallely. I also managed to include operand forwarding with cross pipeline forwarding and pipeline swap compensation! What an act...
August 26, 2025 at 1:36 AM
YES!!! Ladies and gentlemen, my first functional super scalar CPU! It still lacks the jump/branch and memory operations but i managed to get the first operations run parallely. I also managed to include operand forwarding with cross pipeline forwarding and pipeline swap compensation! What an act...
Did a lil in the super scalar experimental department with the simple 16 bit ISA. Inspired by the Motorola 68060 i started building it with two pipelines, one supporting the full ISA (A) while the second (B) won't have a Mul/Div and Jump/Branch unit. They can even swap instructions when needed!
August 25, 2025 at 1:21 AM
Did a lil in the super scalar experimental department with the simple 16 bit ISA. Inspired by the Motorola 68060 i started building it with two pipelines, one supporting the full ISA (A) while the second (B) won't have a Mul/Div and Jump/Branch unit. They can even swap instructions when needed!
Some progress! I managed in a colab with a comrade to develop the MMU for the 16 bitter and general MMU. It is currently primitive with one level PT with 10 bit page index but it got a TLB, page reloading and pagefault! Still needs reset, PID, ... but we will introduce that in the next iterations
August 16, 2025 at 12:54 AM
Some progress! I managed in a colab with a comrade to develop the MMU for the 16 bitter and general MMU. It is currently primitive with one level PT with 10 bit page index but it got a TLB, page reloading and pagefault! Still needs reset, PID, ... but we will introduce that in the next iterations
Need to take a detour from the 16 bitter for a short while, got into something with a comrade about "a RISC approach to CISC". I basically designed a simple FSM for variable instruction length decoding without microcode and came up with a stupid ISA idea and way too much support for it
August 9, 2025 at 8:59 PM
Need to take a detour from the 16 bitter for a short while, got into something with a comrade about "a RISC approach to CISC". I basically designed a simple FSM for variable instruction length decoding without microcode and came up with a stupid ISA idea and way too much support for it
another sneak peek on my 16 bitter, just added the last memory instructions and fixed JMOV, a more generalized RET i love to use in my ISAs with interrupt support. Next on the agenda: finishing interrupts and the FPU, later on starting with the MMU
July 30, 2025 at 12:56 PM
another sneak peek on my 16 bitter, just added the last memory instructions and fixed JMOV, a more generalized RET i love to use in my ISAs with interrupt support. Next on the agenda: finishing interrupts and the FPU, later on starting with the MMU
Doesn't look like much changed but the 16 bitter finally executed the first instructions (some test instructions and Fibonacci). The pipeline with partial forwarding works and i managed to write code for it in my magic assembler after some bug extermination. Next on the list: branch and jump unit
July 16, 2025 at 12:27 AM
Doesn't look like much changed but the 16 bitter finally executed the first instructions (some test instructions and Fibonacci). The pipeline with partial forwarding works and i managed to write code for it in my magic assembler after some bug extermination. Next on the list: branch and jump unit
Small sneak peek of the logisim CPU based on my 16 bit RISC ISA. First CPU of mine doing only partial pipeline forwarding (important for multi cycle execution units like my FPU). Still a lot of things to do like the ring modes, interrupts, MMU, branch unit, ... but the basic structure stands!
July 13, 2025 at 12:06 AM
Small sneak peek of the logisim CPU based on my 16 bit RISC ISA. First CPU of mine doing only partial pipeline forwarding (important for multi cycle execution units like my FPU). Still a lot of things to do like the ring modes, interrupts, MMU, branch unit, ... but the basic structure stands!
Okay, char set ready and already converted into my assembler data format to be used! Next thing on my list display it on my terminal engine and fixing it
July 3, 2025 at 12:17 AM
Okay, char set ready and already converted into my assembler data format to be used! Next thing on my list display it on my terminal engine and fixing it
Ah wait, corrected the tilde. Now it should be better
July 2, 2025 at 1:01 PM
Ah wait, corrected the tilde. Now it should be better
Managed to finish my 8 x 8 pixel per character ASCII char set for my terminal engine and general GPU stuff. Not perfect but eh, should do the job for now. If there is some interest then i can publish it on github under open source with a .coe file and if wished also in other formats!
July 2, 2025 at 12:59 PM
Managed to finish my 8 x 8 pixel per character ASCII char set for my terminal engine and general GPU stuff. Not perfect but eh, should do the job for now. If there is some interest then i can publish it on github under open source with a .coe file and if wished also in other formats!
Some good news: the URCL front end of my custom universal compiler should be ready within this weekend. Next on the plan after that will be the optimization modules and """"back end"""". Meanwhile the hardware department is also progressing, finished parts of the interconnect for the 4-way OoOE CPU
May 24, 2025 at 12:12 AM
Some good news: the URCL front end of my custom universal compiler should be ready within this weekend. Next on the plan after that will be the optimization modules and """"back end"""". Meanwhile the hardware department is also progressing, finished parts of the interconnect for the 4-way OoOE CPU
Okay, got a tiny terminal driver (2 KByte RAM, 62 LUTs, 67 FFs) for general purpose stuff, especially when for all cases when i am running out of BRAM. Still got a lot space left so i might be able to expand it to a sprite engine. The char set is custom and still in the making
May 3, 2025 at 12:03 AM
Okay, got a tiny terminal driver (2 KByte RAM, 62 LUTs, 67 FFs) for general purpose stuff, especially when for all cases when i am running out of BRAM. Still got a lot space left so i might be able to expand it to a sprite engine. The char set is custom and still in the making
Going insane with seeing system verilog and c++ code all day. So back to the roots with logisim! Restarted working on my 4-way OoOE CPU again, here a screenshot with the register renaming, res. stations and half the execution units ready!
April 25, 2025 at 12:13 AM
Going insane with seeing system verilog and c++ code all day. So back to the roots with logisim! Restarted working on my 4-way OoOE CPU again, here a screenshot with the register renaming, res. stations and half the execution units ready!
A small example of the used code format for my assembler. It is really comfortable and the fact that i can use it with any ISA is calming my normally hex programming soul. Finally my cross porting nightmares found an end
April 20, 2025 at 8:57 PM
A small example of the used code format for my assembler. It is really comfortable and the fact that i can use it with any ISA is calming my normally hex programming soul. Finally my cross porting nightmares found an end
The assembler works, but don't look at it the wrong way... Next steps are stability and some more cool features for my assembler format
April 19, 2025 at 1:51 AM
The assembler works, but don't look at it the wrong way... Next steps are stability and some more cool features for my assembler format
Fully parameterizable VGA driver with double buffering and parameterizable buffer configuration! I am currently on building the execution units, the first one (an advanced blitter/sprite engine) is on the making. People get addicted by drugs and social media, i get addicted to green bars and numbers
March 26, 2025 at 12:24 AM
Fully parameterizable VGA driver with double buffering and parameterizable buffer configuration! I am currently on building the execution units, the first one (an advanced blitter/sprite engine) is on the making. People get addicted by drugs and social media, i get addicted to green bars and numbers
Finally finished the tiny 8 bit RISC #logisim implementation with two cores. I won't put it on an FPGA since it is inefficient but it shows that you can make any CPU multicore with a little memory subsystem magic. It can synchronise via an address mapped address reservation mechanism (address lock)
January 31, 2025 at 12:11 AM
Finally finished the tiny 8 bit RISC #logisim implementation with two cores. I won't put it on an FPGA since it is inefficient but it shows that you can make any CPU multicore with a little memory subsystem magic. It can synchronise via an address mapped address reservation mechanism (address lock)