Looking good on Intel too, improving measured latency by ~6.8 ns, or 19-20 cycles

Yeah. I was more surprised ARL didn't dynamically adjust the SNCU/D2D clock, even with XMP disabled. They clearly had that capability in MTL and the uncores are very similar.

Still ARL idle power is just fine for a desktop platform, so maybe they didn't bother.

Yep, that was a fun one. Loved the quirky Northbridge with its separate paths for CPU and GPU memory accesses. I should boot that system back up sometime and check the NB power states too.

That's for Cortex A78. I have not tried on anything else. With officially documented events, 0x26 (iTLB access) can infer op cache misses at the 32B fetch window granularity. A78's op cache is virtually addressed, and doesn't require TLB lookup on a hit.

Ooh, thanks for the link! I looked on Intel's PDFs and sites, and didn't find anything on LNL/ARL. I will check this out

Remember that after Bulldozer, it took AMD five years to change direction. And even with Zen, that's only a foundation. They built on that for several more years before really threatening Intel

Exactly. It's like getting one move in a turn based game and having a board call whether you won or lost based on the results of that single turn.

I also think an engineer should lead the company because they can appreciate the technical challenges/sniff out BS, and Pat Gelsinger is an engineer.

x.com/lamchester/s... I figured some of it out for Zen 2. Events 7 and 0x47 correspond to traffic on the two DDR4 channels. Never got around to doing that for newer Zen generations though

:D That was a fun article to write, though I spent way too much free time poking around and gathering data

(bottom is from the Zen 4 PPR)
Zen 2 used eight bits, letting you select any combination of logical SMT threads within a CCX for L3 performance monitoring. More flexible, but would take too many bits with Zen 3's larger CCXes.