Chapter 1. Art of Electronics Complete - Review finished!

Finished reading:
- Teach Yourself Physics
Currently studying:
- Students' Guide to Maxwell's Equations

⚡ Starting my next FPGA project: building an Ethernet stack from scratch.
Learning and pulling design lessons from Mastering FPGA Chip Design: For Speed, Area, Power, and Reliability by Kevin Hubbard.

I’ll post progress updates in the replies. #FPGA #Ethernet #LearningInPublic

Project log: STM32F407 driver build is complete ✅ (for now)
Wrote my own GPIO + SPI drivers from scratch, debugged MODF, and built a working TX demo.
Learned a lot about creating a driver API

SPI driver update: Hit MODF in master mode 🫠
Fix = Set SSI = 1 to tie NSS to +VCC internally. Because the SSI bit influences NSS state when SSM = 1. By default, SSI = 0, so NSS will be pulled low, not acceptable in non multi master mode.
Lesson learned.

Tonight’s build: STM32F407 SPI2 TX demo
PB13=SCLK, PB15=MOSI (AF5), master, 8-bit frames, CPOL=0/CPHA=0, SSM=1, fSCLK≈8 MHz.
Transmitting "Hello World" over MOSI ✅
Next: enable NSS/MISO, add RX path with DMA/IRQ, and handle OVR correctly.
#STM32 #STM32F4 #SPI #Embedded #BareMetal #C #MCU #DriverDev

Milestone: GPIO external interrupts on STM32F407
Configured EXTI lines + NVIC, rising/falling edge demo, and a simple timer-guard for debounce. Next: tidy ISR helpers and document latency/throughput notes.
#STM32 #STM32F4 #Embedded #BareMetal #C #MCU #DriverDev

Roadmap: STM32F407 Driver Layer (bare-metal, no HAL)

✅ GPIO

🔜 SPI → I²C → UART
Goals: reusable driver API, clean IRQ/DMA paths, easy porting across STM32F4. Follow the thread below for build logs and code gists.

github.com/MicoMigs/STM...

#STM32 #STM32F4 #Embedded #BareMetal #C #MCU #DriverDev

Status: Building out an SPI driver for the STM32F407. Defined config & handle structs to manage device mode, bus config, clock speed, frame format, and control bits (CPOL/CPHA/SSM). Getting closer to a clean abstraction for SPI communication. #EmbeddedSystems #STM32 #DriverDev