the eight stages of grief:
- Prefetch
- Fetch
- Align
- Decode
- Queue
- Register
- Execute
- Write

protip: 8 pipeline stages means even in the riscv-formal traces you can see the processor crying on branches.

[lofty's cpu (nightcore)]

So, the thing I'm having issues with, more specifically, is the load/store bus interface. I have to output the access on the bus, twiddle my thumbs until it completes, and then retire it, and this is kind of a nightmare to fit into my code. Maybe I designed myself into […]

[lofty's cpu (nightcore)]

my stated goal for nightcore is instruction fusion maximalism, and I'm continuing with that, but I don't think I'd appreciated just how much register clobbering RV does. I've resigned myself to needing a second register file write port...

[lofty's cpu (nightcore)]

current status is that my CPU passes most of the riscv-formal RV32I test cases, but I don't have loads and stores implemented yet.

[re: "RAM price hikes wouldn't matter if we wrote more efficient software"]

@0x0ade@void.0x0a.de I think what I've come to learn is that engineer time is very often the factor that we humans actually optimise for. I can't remember who talked about it, but we optimise things only when things […]

[lofty's cpu (nightcore)]

So anyway in light of the joke I made a while ago I officially named the project nightcore :p

Did you know that CPU buses are a fuck? Like, seriously, there are a bajillion different CPU buses ranging from "very dumb" to "juggle four transactions at once :3" and […]

@coral@empty.cafe no, I know how tagged unions work :p

I want to see what the output looks like, because if I have a failing testcase I have to deal with the chewed-up-and-spat-out verilog, not the beautiful BSV.

@coral@empty.cafe how badly does it mangle these types to fit hardware? :p

@the_art_of_giving_up@mastodon.social Verilog is also very good at that

@xeno@hexokina.se this is how one filters their followers :p

[answer to above]

trust embedded on the sand