It runs the same C-code, but « slower ».

Slower as in « more clock cycles », but these clock cycles can be much shorter, and some instruction can take less clock cycles, because the combinational path is split in shorter segments

I promised more FPGA shenanigans.
What about a custom RISC-V cpu that can run C code ?

I’ve designed a primitive single cycle RV32Ish (it’s missing a few instr) CPU and implemented it on the DE10-Lite.
It broke me 😂
What a journey it has been from the @shawnhymel.bsky.social FPGA course to this !

…but as a proof of concept, I’m really proud !!

I think I need a soft charging circuit for this output cap though, listen to the coil whine at startup 😂

Vpp is less than 0.1V under a 3W load (10% of target)

Can’t wait for the next steps !! Stay tuned ⚡️

Oh and thanks @ifixit.com for the FixHub!

Hey @ifixit.com, i've been waiting for your answer about my nearly unusable FixHub.

It seems that a concentricity defect between the barrel and the jack input (tested with multiple tips) is causing a really flimsy connection.

I hate to do this... but i've waited long enough, please get back to me