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camel-cdr.bsky.social
@camel-cdr.bsky.social
34 followers 52 following 120 posts
🐘 @camelcdr@tech.lgbt
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camel-cdr.bsky.social
"How NOT To Program
an Out-of-order Vector
Processor" slides are public.

static.sched.com/hosted_files...
October 23, 2025 at 10:51 AM
camel-cdr.bsky.social
Tenstorrent decided to publish the first benchmark data for Ascalon's RVV implementation using the instruction throughput benchmark of my rvv-bench benchmark suite. <3

camel-cdr.github.io/rvv-bench-re...

Overall, the results look really good so far:
September 25, 2025 at 5:49 PM
camel-cdr.bsky.social
The sixth Championship of Branch Prediction (CBP2025) happened a week ago: ericrotenberg.wordpress.ncsu.edu/cbp2025-work...
June 28, 2025 at 6:36 AM
camel-cdr.bsky.social
oh no

> When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the vta and vma bits in vtype.
When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the vta and vma bits in vtype.
May 26, 2025 at 9:39 PM
camel-cdr.bsky.social
May 13, 2025 at 7:58 AM
camel-cdr.bsky.social
May 13, 2025 at 7:58 AM
camel-cdr.bsky.social
Pretty cool, I can only look at my full shell history roughly dating back four to six years.

421399 commands, of which 65985 were unique

Here are my top 10 commands with description:
23489 ls // Should be obvious 12057 .. // cd .. shortcut 9334 ./a.out // I can't be bothered to rename executables 9045 mr // shortcut for make run 7408 // Apparently I like my blank lines 3691 v // vim 3627 bsdn // backup and shutdown 3260 cpp bf.c // From that one time I implemented brainfuck in the c preprocessor 3211 m // shortcut for make 3122 cd /tmp // I abuse the heck out of /tmp
December 27, 2024 at 5:54 PM
camel-cdr.bsky.social
Removing single line comments in multiple lines in parallel with RVV.

If anyone has a good AVX512 solution, please share.

Inspired by this reddit post: www.reddit.com/r/simd/comme...

#RVV #RISC-V #SIMD
/* Note: '\' is '\n' */ 0123456789ABCDEFGHIJKLMNOPQRSTUVWX | vid Line 1# # # ## #\Line2 # #\Line 3 | v0 = input 0000001001010110110000001011000000 | m = vmor(vmseq(v0, '#'), vmseq(v0, '\n')) 000000111223345567777777889AAAAAAA | iota = vslide1down(viota(m)) /* vl-=1 */ 0######\##\ | v1 = vslide1up(vcompress(v0, m), 0) 000000###########\\\\\\\###\\\\\\\ | seg-cp-scan = vrgather(v1, iota) 0000001111111111100000001110000000 | seg-cp-scan == '#' Line 1\Line2\Line 3 | vcompress(v0, seg-cp-scan)
December 27, 2024 at 1:19 AM
camel-cdr.bsky.social
Here are some slightly tricky RVV mask patterns.
'RVV mask tricks' # broadcast nth bit vmand.mm v8, in, mNth vcpop.m t0, v8 sub t0, x0, t0 vmv.v.x v8, t0 # prefix xor viota.m v8, in vand.vi v8, v8, 1 vmsne.vi v8, v8, 0 vmor.mm v0, v8, in # can often be omitted # move nth bit to first vmand.mm v8, in, mNth vcpop.m t0, v8 vmv.v.x v8, t0 vmsof.m v0, v8 # move mask to GPR vmv.x.s t0, v0 # move GPR to mask vmv.s.x v0, t0 # assuming vl<=64, set SEW=64 before # these two should really be dedicated instructions # shift mask up by 1 vslide1up.vx v8, in, x0 vsrl.vi v8, v8, 7 vmadd.vx v0, 2, v8 # shift mask up by 1 vslide1down.vx v8, in, x0 vadd.vv v0, in, in vmacc.vx v0, 128, v8
December 3, 2024 at 9:37 PM