Jörg Mische
@bobbl.bsky.social
FPGA, RISC-V, NoC, hard real-time, lightweight cryptography
QEMU has no user-mode emulation for TriCore, but Infineon's TSIM offers some virtual I/O that can be used instead.
User-mode emulation for TriCore with TSIM and the GNU toolchain
QEMU User-mode Emulation is a practical solution for testing algorithms directly without having to set up a microcontroller system and boot it every time you test. Unfortunately, QEMU only supports fu...
bobbl.github.io
November 13, 2025 at 10:20 PM
QEMU has no user-mode emulation for TriCore, but Infineon's TSIM offers some virtual I/O that can be used instead.
PunyCC finally supports OpenRISC. The branch delay slots were really challenging. But now you can build cross compilers to and from any of the other supported ISAs: x86, ARM Thumb, RISC-V and WASM.
GitHub - bobbl/punycc: Very small self-compiling cross compiler for a subset of C
Very small self-compiling cross compiler for a subset of C - bobbl/punycc
github.com
October 28, 2025 at 11:17 PM
PunyCC finally supports OpenRISC. The branch delay slots were really challenging. But now you can build cross compilers to and from any of the other supported ISAs: x86, ARM Thumb, RISC-V and WASM.
Puny C Compiler, one of the smallest cross compilers in the world, now supports WebAssembly in addition to ARMv6-M, RISC-V RV32IM and Intel x86-32.
GitHub - bobbl/punycc: Very small self-compiling cross compiler for a subset of C
Very small self-compiling cross compiler for a subset of C - bobbl/punycc
github.com
March 13, 2024 at 8:58 PM
Puny C Compiler, one of the smallest cross compilers in the world, now supports WebAssembly in addition to ARMv6-M, RISC-V RV32IM and Intel x86-32.
Reposted by Jörg Mische
January 3, 2024 at 7:47 PM