YosysHQ
@yosyshq.com
The home for the team maintaining Yosys and related Open Source EDA projects.
https://www.yosyshq.com/
Sign up to our newsletter! https://yosyshq.com/newsletter
https://www.yosyshq.com/
Sign up to our newsletter! https://yosyshq.com/newsletter
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join the meeting here: meet.jit.si/yosys-users-...
Join the meeting here: meet.jit.si/yosys-users-...
Newsletter
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blog.yosyshq.com
February 9, 2026 at 3:17 PM
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join the meeting here: meet.jit.si/yosys-users-...
Join the meeting here: meet.jit.si/yosys-users-...
For our 12th Yosys User’s Group we’re inviting your questions! What have you always wanted to ask the team?
- Formal verification
- Synthesis
- Plugins / internals
- How to contribute
- Roadmap
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.
- Formal verification
- Synthesis
- Plugins / internals
- How to contribute
- Roadmap
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.
February 9, 2026 at 3:17 PM
For our 12th Yosys User’s Group we’re inviting your questions! What have you always wanted to ask the team?
- Formal verification
- Synthesis
- Plugins / internals
- How to contribute
- Roadmap
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.
- Formal verification
- Synthesis
- Plugins / internals
- How to contribute
- Roadmap
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.
Reposted by YosysHQ
At RF, your circuit stops being “small” compared to the signal - and everything changes.
New video interview about RF design, VNAs, simulation, and on-chip antennas.
www.youtube.com/watch?v=2xSA...
New video interview about RF design, VNAs, simulation, and on-chip antennas.
www.youtube.com/watch?v=2xSA...
Simulating RF Reality: VNAs, OpenEMS, and an On-Chip Antenna Design with Ghaith
YouTube video by Zero To ASIC Course
www.youtube.com
February 6, 2026 at 11:30 AM
At RF, your circuit stops being “small” compared to the signal - and everything changes.
New video interview about RF design, VNAs, simulation, and on-chip antennas.
www.youtube.com/watch?v=2xSA...
New video interview about RF design, VNAs, simulation, and on-chip antennas.
www.youtube.com/watch?v=2xSA...
Reposted by YosysHQ
The last month of my life: BreakingTTAPs
This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space)
I'll make a video at some point, but some high level details here:
This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space)
I'll make a video at some point, but some high level details here:
December 4, 2025 at 2:51 PM
The last month of my life: BreakingTTAPs
This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space)
I'll make a video at some point, but some high level details here:
This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space)
I'll make a video at some point, but some high level details here:
Reposted by YosysHQ
What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more!
Check this article for all the links: zerotoasiccourse.com/post/excited...
#opensource #ASIC #tools
Check this article for all the links: zerotoasiccourse.com/post/excited...
#opensource #ASIC #tools
November 24, 2025 at 11:54 AM
What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more!
Check this article for all the links: zerotoasiccourse.com/post/excited...
#opensource #ASIC #tools
Check this article for all the links: zerotoasiccourse.com/post/excited...
#opensource #ASIC #tools
Ever wanted to try adding formal verification to your project but it seemed too hard or expensive to get started? In this video @mattvenn.net Venn shows you an easy way to get up and running with our open source tools and GitHub actions!
youtu.be/Tn5wCOhzfvs
#Verification #Formal #OpenSource
youtu.be/Tn5wCOhzfvs
#Verification #Formal #OpenSource
Formal Verification Adoption Made Easy - DVWorld Club
YouTube video by YosysHQ
youtu.be
October 31, 2025 at 10:03 AM
Ever wanted to try adding formal verification to your project but it seemed too hard or expensive to get started? In this video @mattvenn.net Venn shows you an easy way to get up and running with our open source tools and GitHub actions!
youtu.be/Tn5wCOhzfvs
#Verification #Formal #OpenSource
youtu.be/Tn5wCOhzfvs
#Verification #Formal #OpenSource
Reposted by YosysHQ
You have just 10 days left to get your #ASIC design submitted to our TTSKY25b shuttle!
There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185!
Get started here: tinytapeout.com
There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185!
Get started here: tinytapeout.com
Tiny Tapeout - Tiny Tapeout
From idea to chip design in minutes! Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip.
tinytapeout.com
October 31, 2025 at 9:59 AM
You have just 10 days left to get your #ASIC design submitted to our TTSKY25b shuttle!
There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185!
Get started here: tinytapeout.com
There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185!
Get started here: tinytapeout.com
Starting in just over an hour!
meet.jit.si/yosys-users-...
meet.jit.si/yosys-users-...
Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
October 9, 2025 at 2:56 PM
Starting in just over an hour!
meet.jit.si/yosys-users-...
meet.jit.si/yosys-users-...
Join us tomorrow at 18:00 CEST!
Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
October 8, 2025 at 3:39 PM
Join us tomorrow at 18:00 CEST!
Reposted by YosysHQ
this is me!! very much looking forward to presenting :3 please come join if you're interested in spaceflight/fault-tolerant computing or EDA algorithms! #yosys #eda
Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
October 1, 2025 at 11:40 AM
Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
September 29, 2025 at 10:54 AM
Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
Reposted by YosysHQ
Teaching processor design at Telecom Nancy
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...
September 22, 2025 at 4:36 PM
Teaching processor design at Telecom Nancy
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...
We are hiring! Both technical and admin, please take a look at our jobs page!
www.yosyshq.com/jobs
#jobs #hire
www.yosyshq.com/jobs
#jobs #hire
Jobs
Employee Profile: Synthesis or Formal Verification Developer at YosysHQ
You might know YosysHQ from our many Open Source EDA Projects. We are the maintainers of Yosys and the accompanying Open Source ...
www.yosyshq.com
September 18, 2025 at 3:28 PM
We are hiring! Both technical and admin, please take a look at our jobs page!
www.yosyshq.com/jobs
#jobs #hire
www.yosyshq.com/jobs
#jobs #hire
In our latest guest blog post, Matt Young introduces an Automated Triple Modular Redundancy EDA Flow for Yosys!
blog.yosyshq.com/p/tamara-tow...
blog.yosyshq.com/p/tamara-tow...
TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys
This is a guest blog post by Matt Young\n# Foreword Although I’m a computer scientist by education, I’ve always been interested in space since I was a kid. For a long time, I had simply forgotten abou...
blog.yosyshq.com
August 25, 2025 at 11:09 AM
In our latest guest blog post, Matt Young introduces an Automated Triple Modular Redundancy EDA Flow for Yosys!
blog.yosyshq.com/p/tamara-tow...
blog.yosyshq.com/p/tamara-tow...
Reposted by YosysHQ
Isle 🏝️ is my new #FPGA project.
Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...
Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...
August 1, 2025 at 8:14 AM
Isle 🏝️ is my new #FPGA project.
Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...
Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...
Reposted by YosysHQ
Want to help build a crowdsourced microcontroller?
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
July 25, 2025 at 10:57 AM
Want to help build a crowdsourced microcontroller?
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
Reposted by YosysHQ
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
June 9, 2025 at 11:50 AM
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
June 9, 2025 at 11:50 AM
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
Reposted by YosysHQ
Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer
June 4, 2025 at 3:47 PM
Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer
Reposted by YosysHQ
June 3, 2025 at 12:23 PM
Reposted by YosysHQ
IHP25b - our 4th open source chip with IHP is now open for digital design submissions!
We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!
We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!
April 25, 2025 at 10:08 AM
IHP25b - our 4th open source chip with IHP is now open for digital design submissions!
We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!
We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!
Reposted by YosysHQ
We’re close to making key decisions about future shuttles—and we want your input! 💬
What features matter most? What’s your price ceiling?
Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...
🎁 One respondent will win a beautiful 150mm silicon wafer!
What features matter most? What’s your price ceiling?
Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...
🎁 One respondent will win a beautiful 150mm silicon wafer!
April 15, 2025 at 8:40 AM
We’re close to making key decisions about future shuttles—and we want your input! 💬
What features matter most? What’s your price ceiling?
Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...
🎁 One respondent will win a beautiful 150mm silicon wafer!
What features matter most? What’s your price ceiling?
Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...
🎁 One respondent will win a beautiful 150mm silicon wafer!
Reposted by YosysHQ
Reposted by YosysHQ
Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...
Release nextpnr 0.8 · YosysHQ/nextpnr
Remove nextpnr-gowin; replaced by Gowin support in nextpnr-himbaechel
Remove unmaintained FPGA interchange support
Updated and reworked CMake build system
Himbaechel: Numerous improvements to Gowin...
github.com
March 24, 2025 at 10:37 AM
Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...
Join us in a few hours for a talk about ASIC synthesis with Yosys!
18:00 CET / 22:30 IST / 09:00 PT
meet.jit.si/yosys-users-...
18:00 CET / 22:30 IST / 09:00 PT
meet.jit.si/yosys-users-...
February 20, 2025 at 1:17 PM
Join us in a few hours for a talk about ASIC synthesis with Yosys!
18:00 CET / 22:30 IST / 09:00 PT
meet.jit.si/yosys-users-...
18:00 CET / 22:30 IST / 09:00 PT
meet.jit.si/yosys-users-...