Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

Join us in a few hours for a talk about ASIC synthesis with Yosys!

18:00 CET / 22:30 IST / 09:00 PT

meet.jit.si/yosys-users-...

It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...

This time we'll be turning to #ASIC synthesis with our own Emil Jiří Tywoniak.

Looking for a tiny RISC-V core that scales with your needs?

We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-...

Now it's been silicon proven on @tinytapeout.com !

www.linkedin.com/posts/meinha...

Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes!

Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST