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instlatx64.bsky.social
InstLatX64
@instlatx64.bsky.social
x86/x64, SIMD, #AVX512, "Aha!" moments.
I have been writing code since 1986.

Budapest, Europe
https://instlatx64.github.io/InstLatx64/
#AMD refreshed the "Revision Guide for AMD Family 19h Models 10h-1Fh Processors" 57095 to v1.05 pdf
( #Genova #Zen4 B0 CPUID A10F11 #EPYC )
docs.amd.com/v/u/en-US/57...
November 14, 2025 at 2:15 PM
#AMD refreshed the "Revision Guide for AMD Family 19h Models A0h-AFh Processors" 57926 to v1.05 pdf
( #Bergamo #Zen4c A0 CPUID AA0F02 #EPYC )
docs.amd.com/v/u/en-US/57...
November 14, 2025 at 2:15 PM
#Intel released the 60th edition of the ISA Extensions Reference with official announcement of #AVX10 and #APX support on #NovaLake, and FP8 type clarifications.
Download:
cdrdv2-public.intel.com/869288/31943...
#DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf
November 13, 2025 at 8:07 AM
Today I learned: At least 3 #AVX512 levels were planned, but they never released:
#AVX512QVNNI - byte form of 4VNNIW, it would extinct with KNM/MIC;
#AVX512DFMA - VDF[,n]MADD[P,S][S,D] - I have no idea what the difference between FMA & DFMA;
#AVX512BITALG2 - this is the most interesting for me;
1/3
November 11, 2025 at 1:39 PM
November 9, 2025 at 8:44 PM
#AMD #Zen6 znver6 ISA:
- #AVX512_BMM (CPUID.80000021.EAX[23], VBMACOR16x16x16, VBMACXOR16x16x16, VBITREV)
- #AVX512_FP16
- #AVX_NE_CONVERT
- #AVX_IFMA
- #AVX_VNNI_INT8
Source:
sourceware.org/pipermail/bi...
#AMD CPUID refresh:
-- CPUID B80F00 is #Zen6 [1]
-- #Zen5c #Sorano CPUID is B10F00 (#EPYC 8005, SP6 socket) [2],[3]
-- #Zen5 #Grado CPUID is B40F40 (EPYC 4005, AM5 socket) [4]
GitHub:
github.com/InstLatx64/I...
1/2
November 8, 2025 at 1:11 AM
Visualised AMD-SB-7055 issue on a #Zen5 #AMD #Ryzen 9 9950X. The zeroed #RDSEED rate can exceed the 3% under concurrent execution...
www.amd.com/en/resources...
November 7, 2025 at 10:38 AM
#Intel refreshed the "Intel Virtualization Technology for Directed I/O Architecture Specification" pdf to 5.1
cdrdv2-public.intel.com/868911/D5139...
November 7, 2025 at 9:21 AM
#AMD CPUID refresh:
-- CPUID B80F00 is #Zen6 [1]
-- #Zen5c #Sorano CPUID is B10F00 (#EPYC 8005, SP6 socket) [2],[3]
-- #Zen5 #Grado CPUID is B40F40 (EPYC 4005, AM5 socket) [4]
GitHub:
github.com/InstLatx64/I...
1/2
October 29, 2025 at 6:53 PM
#Intel released the 89th edition of the Software Developer’s Manuals with a new SEAM, and completely rewritten CPUID (with domain info) section:
All-in-One:
cdrdv2-public.intel.com/868137/32546...
Changes v81:
cdrdv2-public.intel.com/868136/25204...
UDB (opcode D6h) canonized
October 29, 2025 at 9:51 AM
Not a clear commitment, but a very good sign: #APX appeared in Mark Papermaster's presentation
#OCP2025 #AMD #x86EAG
www.amd.com/en/blogs/202...
youtu.be/Z36PjXFBmig?...
October 27, 2025 at 11:36 AM
Unfortunately, #Intel does not answer openly Game.Keeps.Loading 's question regarding #NovaLake ISA:
community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-APX-ACX-10-2/m-p/1723564#M86387

#APX #AVX10_1 #AVX10_2 #AVX512
October 27, 2025 at 9:21 AM
This contradicts the earlier info:
- homogenized, 512b-only #AVX10
- oneDNN 3.9 release note [1]
- 2:1 #PantherCove : #ArcticWolf die size
and the common sense, without #APX -capable desktop SKUs, APX will be rare on servers too...
[1]: bsky.app/profile/inst...
October 22, 2025 at 1:23 PM
#Intel #VPMM is back in the 7th edition of "Intel® TDX Module Base Architecture Specification (What Changed)".
Probably just a documentation bug.
cdrdv2-public.intel.com/867556/intel...
October 22, 2025 at 12:21 PM
October 16, 2025 at 2:50 PM
#AMD & #Intel unified future instructions:
#FRED #AVX10 #ChkTag #ACE (=ACE (Advanced Matrix Extensions for Matrix Multiplication): www.amd.com/en/blogs/202...
October 14, 2025 at 7:17 AM
What happened to the SiSoftware Sandra? Why hasn't a new one been released since October 2023?
www.sisoftware.co.uk
SiSoftware – Windows, Android, GPGPU, CUDA, OpenCL, analysers, diagnostic and benchmarking apps
www.sisoftware.co.uk
October 13, 2025 at 2:39 PM
The Netwide Assembler 3.01 is ready and supports the full #DiamondRapids and #NovaLake instruction sets:
nasm.us
#AVX10_2 #AVX10_VNNI_INT #APX #AMX_FP8 #AMX_TF32 #AMX_COMPLEX #AMX_AVX512 #AMX_MOVRS
October 11, 2025 at 10:07 AM
New #AMD CPUID dump:
64-Core #ThreadripperPro 9985WX ( #ShimadaPeak, #Zen5) B00F81
GitHub:
github.com/InstLatx64/I...
October 10, 2025 at 9:58 AM
#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors" 58251 to v1.10 pdf
(#Turin #Zen5 C1 CPUID B00F21 #EPYC)
docs.amd.com/v/u/en-US/58...
October 8, 2025 at 8:17 AM
#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 10h-1Fh Processors" 58730 to v1.30 pdf
(#TurinD #Zen5c B0 CPUID B10F10 #EPYC)
docs.amd.com/v/u/en-US/58...
October 8, 2025 at 8:16 AM
#Intel #Pantherlake #CougarCove/#Darkmont differences over the 18A process, so far:
- ISA additions (CGC/DMR)
- Better frontend/branch prediction (CGC/DMR)
- P21 bounded insts (CLMUL, GF2MUL?) doubled throughput (DMT)
- 19 -> 17 clks L2 latency (SMT->DMT)
October 6, 2025 at 12:06 PM
#Intel re-released the 59th edition of the ISA Extensions Reference with #USER_MSR clarification:
Download:
cdrdv2-public.intel.com/865891/31943...
#DiamondRapids #NovaLake #WildcatLake
#PantherCove #CoyoteCove #ArcticWolf
October 5, 2025 at 11:28 AM
#VisualStudio2026 18.0.0 Insider implements the so far missing #AVX10_VNNI_INT instructions too.
#DiamondRapids #NovaLake
October 3, 2025 at 9:28 AM