As a computer engineer who has spent half a decade working with caches at Intel and Sun, I’ve learnt a thing or two about cache-coherency. This was one of the hardest concepts to learn back in coll…

Posts about cache-coherent written by chipressian

In the previous post, we discussed about handling non-atomic requests in directory based MSI protocol by stalls. In cache controller transient states such as “IS-D”, “IM-A” and “SM-A”, we could allow forwarded request messages to make progress without stalling, at the expense of adding more transient states. For example, when a cache controller has a line in State “IS-D” and receives an Inv message, it processes the request and changes the line’ state to “IS-D-I”, indicating the cache controller should change the line state to I after the “GetS” transaction completes.

Just like snooping based protocols, directory based cache coherence protocol has to handle non-atomic requests in real world implementations. We start from the a directory based MSI base model, and discuss one solution on non-atomic requests handling. Base Model In directory based MSI protocol, there are 3 message types: Request messages, including GetS, GetM, PutM and PutS Forwarded request messages, including Fwd-GetS, Fwd-GetM, Inv (Invalidation), and Put-Ack…

In the previous post, we discussed non-zero delay from coherence requests to responses. However, coherence requests may also be non-atomic: a coherence request may not be instantly ordered when it is issued by a cache controller. For example, if there is a request queue between a cache controller and the system bus, coherence request atomicity is no longer guaranteed, and this is a fairly common implementation.

In cache coherence protocol implementation, designers must properly handle non-atomic operations, since coherence transactions cannot complete instantly. We start from the well-known snooping based…

To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to coherence shared memory systems. In the world of computer architecture, memory reads (or loads) permanently change processors’ …