Mike Bell
@rebelmike.bsky.social
Electronics tinkerer, narrowboater, puzzle hunter, board gamer and occasional geocacher.
Also on fedi @mike@rebel-lion.uk
Also on fedi @mike@rebel-lion.uk
I designed a thing!
It's a CPU module for a possible RISC-V hackable computer.
It's a CPU module for a possible RISC-V hackable computer.
October 27, 2025 at 10:57 PM
I designed a thing!
It's a CPU module for a possible RISC-V hackable computer.
It's a CPU module for a possible RISC-V hackable computer.
Shape wise, I had been thinking more rounded - this is the current state of the CPU module (most things not even placed yet):
October 26, 2025 at 9:49 AM
Shape wise, I had been thinking more rounded - this is the current state of the CPU module (most things not even placed yet):
Spot the flaw in the plan...
October 9, 2025 at 7:17 PM
Spot the flaw in the plan...
Well that escalated quickly
September 26, 2025 at 6:15 PM
Well that escalated quickly
Well, it blinks.
The whole you have to unplug it from your computer and plug it into an SD card slot that doesn’t act as an SD host to run the design thing may get old rather quickly.
The whole you have to unplug it from your computer and plug it into an SD card slot that doesn’t act as an SD host to run the design thing may get old rather quickly.
September 25, 2025 at 7:14 PM
Well, it blinks.
The whole you have to unplug it from your computer and plug it into an SD card slot that doesn’t act as an SD host to run the design thing may get old rather quickly.
The whole you have to unplug it from your computer and plug it into an SD card slot that doesn’t act as an SD host to run the design thing may get old rather quickly.
Just received a rather tiny dev board. USB-C connector for scale.
September 25, 2025 at 6:45 PM
Just received a rather tiny dev board. USB-C connector for scale.
Let’s see how these test ducks do
September 20, 2025 at 4:47 PM
Let’s see how these test ducks do
To the left are flip-flop cells from the standard library, which store the value of the counter at each clock. Then the adders compute the incremented value ready for the next clock.
It works in simulation, so I'll just have to wait 8 months or so to see if it works in silicon!
It works in simulation, so I'll just have to wait 8 months or so to see if it works in silicon!
September 6, 2025 at 6:19 PM
To the left are flip-flop cells from the standard library, which store the value of the counter at each clock. Then the adders compute the incremented value ready for the next clock.
It works in simulation, so I'll just have to wait 8 months or so to see if it works in silicon!
It works in simulation, so I'll just have to wait 8 months or so to see if it works in silicon!
Being able to draw a structure, and then have it do maths, is so cool.
My first foray into building logic at the lowest level - I've made a 16-bit counter.
The green highlighted cell is my very own half adder, which is repeated 16 times going off the top of the image.
My first foray into building logic at the lowest level - I've made a 16-bit counter.
The green highlighted cell is my very own half adder, which is repeated 16 times going off the top of the image.
September 6, 2025 at 6:19 PM
Being able to draw a structure, and then have it do maths, is so cool.
My first foray into building logic at the lowest level - I've made a 16-bit counter.
The green highlighted cell is my very own half adder, which is repeated 16 times going off the top of the image.
My first foray into building logic at the lowest level - I've made a 16-bit counter.
The green highlighted cell is my very own half adder, which is repeated 16 times going off the top of the image.
Totally normal development process:
August 30, 2025 at 9:13 PM
Totally normal development process:
Watching the #Micropython test suite running on TinyQV, my Risc-V SoC. An increasing number of tests pass 😅
With the #TinyTapeout competition using it, I'm trying to make sure there's no lurking issues!
With the #TinyTapeout competition using it, I'm trying to make sure there's no lurking issues!
July 27, 2025 at 4:39 PM
Watching the #Micropython test suite running on TinyQV, my Risc-V SoC. An increasing number of tests pass 😅
With the #TinyTapeout competition using it, I'm trying to make sure there's no lurking issues!
With the #TinyTapeout competition using it, I'm trying to make sure there's no lurking issues!
Thank you @johnspiers.co.uk and all of Gigspanner Big Band for a great show in Cheltenham this evening.
Wonderful music, I think it was the best of your shows we’ve been to yet!
Wonderful music, I think it was the best of your shows we’ve been to yet!
July 23, 2025 at 10:55 PM
Thank you @johnspiers.co.uk and all of Gigspanner Big Band for a great show in Cheltenham this evening.
Wonderful music, I think it was the best of your shows we’ve been to yet!
Wonderful music, I think it was the best of your shows we’ve been to yet!
Hmm, may have jumped to conclusions that this is bad - here's the and2 from the library doing the same thing. They are different, but there's not that much in it...
June 27, 2025 at 11:19 PM
Hmm, may have jumped to conclusions that this is bad - here's the and2 from the library doing the same thing. They are different, but there's not that much in it...
And probably more concerningly, it's drawing current while in this state - as I understand it this is why CMOS is good, the complementary MOSFETs minimise the transition time where current flows.
June 27, 2025 at 10:16 PM
And probably more concerningly, it's drawing current while in this state - as I understand it this is why CMOS is good, the complementary MOSFETs minimise the transition time where current flows.
And here's the simulation - it does work but you can see strange voltage fluctuations when A is falling.
June 27, 2025 at 10:12 PM
And here's the simulation - it does work but you can see strange voltage fluctuations when A is falling.
I was interested to see what happened if you tried making cells like that in sky130. So here's a (not particularly good) AND gate in magic:
June 27, 2025 at 10:12 PM
I was interested to see what happened if you tried making cells like that in sky130. So here's a (not particularly good) AND gate in magic:
It’s pretty basic at the moment, but I’ve got an fft visualisation and mp3 decode working.
June 14, 2025 at 10:15 PM
It’s pretty basic at the moment, but I’ve got an fft visualisation and mp3 decode working.
Great to see Blackbeard’s Tea Party again, and lovely to chat with them in the bar after the gig!
April 10, 2025 at 10:45 PM
Great to see Blackbeard’s Tea Party again, and lovely to chat with them in the bar after the gig!
Been having lots of fun with @charlie.daft.games‘s Red Alert port for RP2350. I’ve got it working with my HSTX driver and just got PWM sound working as well!
March 28, 2025 at 6:07 PM
Been having lots of fun with @charlie.daft.games‘s Red Alert port for RP2350. I’ve got it working with my HSTX driver and just got PWM sound working as well!
Implemented interlaced modes, and palette support.
There is *just* enough bandwidth for 1080i50 with a 256 colour palette!
That’s full HD moving images using an RP2350 and two APS6404 PSRAMs for the frame buffers.
There is *just* enough bandwidth for 1080i50 with a 256 colour palette!
That’s full HD moving images using an RP2350 and two APS6404 PSRAMs for the frame buffers.
March 23, 2025 at 2:37 PM
Implemented interlaced modes, and palette support.
There is *just* enough bandwidth for 1080i50 with a 256 colour palette!
That’s full HD moving images using an RP2350 and two APS6404 PSRAMs for the frame buffers.
There is *just* enough bandwidth for 1080i50 with a 256 colour palette!
That’s full HD moving images using an RP2350 and two APS6404 PSRAMs for the frame buffers.
And at the somewhat non-standard 1080p30, there’s *just* enough bandwidth from the two PSRAMs to do the same!
March 22, 2025 at 3:54 PM
And at the somewhat non-standard 1080p30, there’s *just* enough bandwidth from the two PSRAMs to do the same!
Using both PSRAMs together we can get enough bandwidth for 720p. Can’t easily write to a back buffer while displaying though as the PSRAM is constantly busy, but can do an image slide show!
The RP2350 decodes the next jpeg from flash during the time the monitor is blank.
The RP2350 decodes the next jpeg from flash during the time the monitor is blank.
March 22, 2025 at 3:34 PM
Using both PSRAMs together we can get enough bandwidth for 720p. Can’t easily write to a back buffer while displaying though as the PSRAM is constantly busy, but can do an image slide show!
The RP2350 decodes the next jpeg from flash during the time the monitor is blank.
The RP2350 decodes the next jpeg from flash during the time the monitor is blank.
Got the double buffer, one in each PSRAM, up and running.
This is 800x600, RGB565, which is fairly close to maxing out the available bandwidth.
This is 800x600, RGB565, which is fairly close to maxing out the available bandwidth.
March 22, 2025 at 12:26 AM
Got the double buffer, one in each PSRAM, up and running.
This is 800x600, RGB565, which is fairly close to maxing out the available bandwidth.
This is 800x600, RGB565, which is fairly close to maxing out the available bandwidth.
My Tiny Tapeout 9 project running on the FPGA board.
Got to have some Bad Apple when testing new hardware!
Got to have some Bad Apple when testing new hardware!
March 21, 2025 at 6:25 PM
My Tiny Tapeout 9 project running on the FPGA board.
Got to have some Bad Apple when testing new hardware!
Got to have some Bad Apple when testing new hardware!
Well this is right on the border line of working, but it does seem to be working!
1080p48 output, running the RP2350 at 1.5V
1080p48 output, running the RP2350 at 1.5V
March 21, 2025 at 11:42 AM
Well this is right on the border line of working, but it does seem to be working!
1080p48 output, running the RP2350 at 1.5V
1080p48 output, running the RP2350 at 1.5V