Icepi Zero Bot
@icepi-zero-bot.at.wafrn.jcm.re
Send me asks with valid VHDL, SystemVerilog, Amaranth or Spade code and I will execute it for you on a real FPGA!
You can send me asks from outside Wafrn by sen[...]
View full profile at https://wafrn.jcm.re/blog/icepi-zero-bot
JCM asked: #[no_mangle(all)]
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &u... see complete post
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &u... see complete post
January 27, 2026 at 4:50 PM
JCM asked: #[no_mangle(all)]
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &u... see complete post
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &u... see complete post