The photomask defines the pattern which should get transferred onto the chip. With this process nodes <10nm can be manufactured without using advanced techniques like multipatterning. This allows increasing the throughput compared to #DUV making it cost efficient.

These mirrors have multiple only nm-thick layers of Si and Mo achieving a reflectivity of ~70%. The mirrors produced by #Zeiss must be extremely precise and are one of the most expensive parts in the tool. The mirrors bundle and align the EUV light which then hits the #photomask.

As light source a tin droplet with a diameter of 30 micron is hit by a CO2 laser pulse generating a plasma. This plasma emits EUV light with a wavelength of 13.5nm. Since EUV light is absorbed by most materials including conventional lenses, the optics in the tool is entirely based on mirrors.

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single blocks as cache, memory, etc. These blocks can be optimized separately and by an advanced BEOL stacked to a 3D chip. More of the concept of CMOS2.0 will be presented here in future.

of the CEFT design will be handling of the interconnects. Therefore the scaling roadmap additionally includes an interconnect roadmap. Major design adaption will be needed, e.g. backside power supply. This leads to the concept of #CMOS2.0. The main idea is a redesign of the full SOC, by optimizing

GAA devices will be potentially be superseded by Forksheet FETs (FSFET) or in other versions of the roadmap directly by complementary FETs (CFET). These geometries are not in detail defined yet, the main idea of a CEFT is to stack a nMOS and a pMOS device allowing further scaling. One main challenge

While in finFETs the gate wraps around the semicond. channel on three sides (forming a fin), in GAA devices the gate surrounds the channel completely. This leads to a better electrostatic control and reduces short-channel effects which allows further scaling.

I already pinned it, thanks a lot :)

Figures in this thread are take from the paper "Global Semiconductor Trends and the Future of EU Chip Capabilities" by Kjeld van Wieringen.
www.researchgate.net/publication/...

What is the future bringing for Europe? The European Chips Act aims to mobilize 43 Billion Euros. Modern foundries are build by Intel and TSMC in Germany. Research is booming. Exciting times are coming.

While many of these foundries are quite successful in their specialized field, they play a minor role in the global semiconductor market. Market shares show clearly that the only European presence is in manufacturing equipment (dominated by ASML) and older nodes.

There are multiple state-of-the-art chip foundries specialized in various technologies like power devices for automotive/solar (Infineon), MEMS (Bosch), etc. but none of these foundries builds modern logic for CPUs or GPUs.

The by far most important Europ. player is #ASML. ASLM is the only manufacturer capable of building EUV lithography tools which are needed for building every single modern chip. These lithography tools are mainly shipped to Taiwan and South Korea, where the majority of high-end nodes are fabricated.

There are three important research centers: #imec (Belgium), #CEA-Leti (France) and #Fraunhofer (Germany). Especially imec is extremely prestigious and probably the most important semiconductor research institution in the world. Research done by imec will be future content of this account.