Variable register allocation and an increase to 10 threads-per-EU are icing on the cake, and it should be much easier to extract performance without massive penalties for higher-complexity vector workloads—if Intel can get their software right, it should be quite competent.

To put it in perspective, consider that Lunar Lake had 2.7× more theoretical throughput relative to available global memory bandwidth versus Battlemage, with less L1$/SLM and L2$ to boot—marginally compute-bound workloads on the latter easily became memory-bound on the former!

Far more true of Plan 9.

girl

@freya.bsky.social, do you have any advice? You seem to be the person that would most likely to have that in my circles.

Somehow I've never read it, despite being deep in rat spaces for a couple years.

In the past couple years since publication, this article has become a bit dated in some details (PipeWire is even more mature now, and I have made changes in my WirePlumber configuration to make everything automatic)—perhaps an update will be in order sometime soon.

I wrote most of my papers in undergrad that way. I wouldn't imagine using Overleaf ever again unless I need to collaborate on another academic paper with others.

*hugs*

I wish to absorb it from you!

Hello!

Mission: Space is four industrial-grade human centrifuges built by Environmental Tectonics Corporation. Add development and all the drama between TWDC and ETC and you get your answer.

Do I count

I *need* to go back

Put GPT-Neo on it

Waow (Based Based Based)

Good luck!