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Arc B580 lighting/shadow artifacting in Space Engineers 2 with light sources
Hello, In Space Engineers 2 I seem to get these weird lighting/shadow artifacts which only appear when lights interact with objects. This is especially noticeable when there are multiple light sources in complex areas. Examples below: Shadow artifacting More artifacting, far awayClose up of previous screenshot, better but it's still incorrect **Information:** * Driver: 32.0.101.6881 * Game is Space Engineers 2 on Steam. * I have also attached an SSU report. I've have made a video demonstrating the issue and have published the test world. The graphics options used in video and screenshots. **Links:** * Video: https://www.youtube.com/watch?v=HfTbhlOelok * World: https://steamcommunity.com/sharedfiles/filedetails/?id=3497753798 Forgot to change it in the video, but this is what happens when the shadow quality setting is set to Medium: Shadows are not present at all. **Steps to reproduce:** 1. Subscribe to the world. 2. In the graphics settings, change the graphics preset to Medium, then change it to "Custom", then change "Shadow Quality" to High or Extreme. 3. Select "New Game", "Worlds", "Intel Arc B580 Graphics Bug Report" and press "Start New Game". **Some notes:** * This issue is only present when the "Shadow Quality" option is set to High or Extreme. Setting this to Medium or Low removes the issue, (however shadows do not exist at all). * This issue is present with raytracing both enabled and disabled. * This issue is seemingly not affected by the sun as seen in the video, only artificial light sources are affected. I haven't noticed any issues with shadows interacting with the sun. * Changing any other setting does not seem to affect the issue, it seems to solely be affected by the Shadow Quality setting. * This has been an issue since I got the GPU. * This issue was present on my old computer when I first got the GPU, (i7 8700, Z370-p, 16gb DDR4). * I have tried DDU and the issue still persists. * I also tried it on a fresh windows install with only the drivers, Steam and Space Engineers 2 installed and the issue still persists.
community.intel.com
June 12, 2025 at 4:56 PM
SPIR-V GLSL imageSize returns 0 on OpenGL 4.6 with Intel UHD Graphics
Hello. I have a test application which copies the width and height of an image2D to a shader storage buffer. The shader I'm using is a SPIR-V compute shader generated from GLSL. I'm using GLSL's imageSize function to get the image dimensions, however it returns 0. I've written an minimum reproducible sample to demonstrate the issue. ### Description I have an HP Victus (7L1J7EA) laptop with an Intel Core i5-12450H and Windows 11 Home 24H2. I can reproduce the issue when every requirement below is met: * The graphics API is OpenGL 4.6 * The GPU is Intel UHD Graphics for 12th Gen Intel Processors (Intel Graphics Driver 31.0.101.4502) * The shader code is a SPIR-V binary generated from GLSL I cannot reproduce the issue when at least one of the requirements below is not met: * The graphics API is Vulkan * The GPU is an AMD Radeon RX 7900 XTX * The GPU is an Intel UHD Graphics 770 (Intel Core i7-13700K) * The GPU is a Nvidia GeForce RTX 3050 * The shader code is a GLSL string I've not found many issues about it but this may be related. ### Steps to reproduce 1. Install GLFW, glad and the Vulkan SDK. 2. Link GLFW and glad to the project. 3. Run ImageSize.bat to generate the SPIR-V binary. 4. Build and run the project. ### Observations Expected console output: Using Intel(R) UHD Graphics Width = 64 Height = 32 Actual console output: Using Intel(R) UHD Graphics Width = 0 Height = 0 This is not a blocking issue since I can pass the dimensions as an uniform but it is still an invalid behavior.
community.intel.com
June 12, 2025 at 2:54 PM
error #5632: **Internal compiler error: specification exception signal raised**
The following MWE module mwe implicit none type T integer :: n end type T type U integer, allocatable :: J(:) end type U contains subroutine aa(tt, uu) implicit none type(T), intent(in) :: tt type(U), optional, intent(in) :: uu(tt%n) contains subroutine internal_of_aa implicit none call absent(tt,uu) end subroutine internal_of_aa end subroutine aa subroutine bb implicit none integer :: ii !$OMP PARALLEL DO do ii = 1, 2 end do !$OMP END PARALLEL DO end subroutine bb end module mwe causes ifx (IFX) 2025.1.0 20250317 to ICE when trying to compile with OpenMP, i.e.: ifx -qopenmp mwe.F90 #0 0x0000000003310581 #1 0x0000000003375357 #2 0x0000000003375485 #3 0x0000150722e3e730 #4 0x000000000254a784 #5 0x000000000255159e #6 0x000000000255142b #7 0x00000000023405b3 #8 0x0000000002787162 #9 0x00000000027818e2 #10 0x000000000236c21b #11 0x00000000024efa9b #12 0x00000000024ef553 #13 0x00000000024e97f2 #14 0x00000000032ae584 #15 0x00000000032abde3 #16 0x0000000003256111 #17 0x0000000003433b58 #18 0x0000150722e295d0 #19 0x0000150722e29680 __libc_start_main + 128 #20 0x000000000308f0ee /tmp/ifx0021656141V07ebn/ifxIQKNuY.i90: error #5632: **Internal compiler error: specification exception signal raised** Please report this error along with the circumstances in which it occurred in a Software Problem Report. Note: File and line given may not be explicit cause of this error. compilation aborted for mwe.F90 (code 3) Dropping -qopenmp makes the compiler behave: undefined reference to `absent_' Any ideas how to work around that issue?
community.intel.com
June 12, 2025 at 8:57 AM
EMIF Location constraint error
Hi I am getting below error while building a Quartus project using Agilex board (DK-DEV-AGI027-RA) with DDR4 component 1 memory. I used following pin constraints, "set_location_assignment PIN_AV33 -to emif_fm_0_mem_mem_ck1][0]" which is correct as per schematic shared in the [https://cdrdv2.intel.com/v1/dl/getContent/819447. Error summary. "Error (175020): The Fitter cannot place logic EMIF_GROUP that is part of External Memory Interfaces (EMIF) IP emif_altera_emif_fm_276_fwujoli in region (226, 333) to (322, 333), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The EMIF_GROUP name(s): EMIF_0_emif_altera_emif_fm_276_fwujoli Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (175005): Could not find a location with: NON_HPS_EMIF (1 location affected) Info (175029): EMIF_GROUP containing J9 Info (175015): The I/O pad emif_fm_0_mem_mem_ck[1][0] is constrained to the location PIN_AV33 due to: User Location Constraints (PIN_AV33) Info (14709): The constrained I/O pad is contained within a pin, which is contained within a ADDR_CMD_GRP, which is contained within this EMIF_GROUP" Can you please check what could be the possible cause of this error. Thanks & regards Madhur
community.intel.com
June 12, 2025 at 8:57 AM