A. Schilling
aschilling.bsky.social
A. Schilling
@aschilling.bsky.social
Editor at hardwareluxx.de
Our server needs an upgrade.
November 15, 2025 at 11:31 AM
The DDR5 market goes crazy right now. On the German market, memory kits are sometimes twice as expensive as they were when they were launched a few months ago (or not available at all). This has also led to some memory manufacturers deciding not to launch new series at all.
November 13, 2025 at 12:55 PM
IBM Quantum Loon and Quantum Nighthawk that are being fabricated at NY CREATES' Albany NanoTech Complex on the 300 mm wafer line.
November 13, 2025 at 7:17 AM
"Tachyum Unveils 2nm Prodigy with 21x Higher AI Rack Performance than the Nvidia Rubin Ultra"

- 1,024 64-bit cores
- up to 6 GHz
- 1 GB L2+L3$
- 24x DDR5-17600
- 48 TB per socket
- 128 lanes of PCIe 7.0
- 1,600 W TDP

But surely ...
November 12, 2025 at 7:16 PM
A good addition to the lineup? AMD did today release the Ryzen 5 7500X3D, which is a very efficient six core CPU, but overpriced compared to the Ryzen 5 7600X3D. We are also not sure whether six cores will still be future-proof in 2025.

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November 12, 2025 at 2:46 PM
My piece on the Financial Analyst Day by AMD yesterday covering the Zen, Epyc and Instinct roadmaps plus near future product releases and details on them.

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November 12, 2025 at 8:31 AM
Needed to disassemble a GeForce RTX 5090 for a reason. The reason is stupid 🤪
October 31, 2025 at 7:51 PM
My colleague visited on of the worldwide five pop-up stores by Intel that are or will be located in Munich, Paris, London, New York and Soul.

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October 30, 2025 at 3:44 PM
This is #Discovery, the next-gen supercomputer run by ORNL and build by HPE. Discovery will use AMD Instinct MI430X accelerators and Epyc "Venice" CPUs.

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October 27, 2025 at 7:16 PM
Single die and dual die implementation of the Maverick-2 by @nextsilicon.com. Single die package is used with the PCIe card while die dual die package sits on the OAM module.
October 25, 2025 at 2:53 PM
Die shot from @nextsilicon.com. But this can't be the Maverick-2, because the aspect ratios look a bit strange, or rather, the HBM PHYs are positioned on the long side here. Or am I wrong? It's been a long week, so apologies in advance!
October 24, 2025 at 4:30 PM
The two Broadcom #Tomahawk 6 102.4T switch chip in two package variants:

Tomahawk 6 112G SerDes (bigger package)
Tomahawk 6 224G SerDes (smaller package)

Source: @servethehome.com.web.brid.gy
October 20, 2025 at 1:14 PM
Researchers at KAUST have stacked six transistors (OxTs and OrTs in an alternating fashion) on top of each other. These stacks consist of 41 layers, fabricated using a 40-step lithography process, each containing 100 devices.
October 20, 2025 at 11:17 AM
OpenAI and Tachyum announce strategic partnership to deploy 10 Quadrillion Watts of Compute Power without deploying any actual Chip made by Tachyum.
October 16, 2025 at 12:51 PM
TSMC Revenue by Node as of Q3 2025.

We should see N2 emerging by Q1 2026 in this graph.
October 16, 2025 at 8:56 AM
Apple M5

- 4x Performance Core
- 6x Efficiency Core
- +15% nT Performance
- +45% higher GPU Performance
- 153 GB/s Memory Interface
- 3 nm Process
October 15, 2025 at 1:41 PM
At 2025 OCP Global Summit AMD shows their Helios rack-scale solution. These are liquid-cooled, 72-GPU racks powering AMD Instinct MI450 Series GPUs, AMD EPYC CPUs (Venice) and do feature integrated UALoE scale-up connectivity.
October 14, 2025 at 1:31 PM
Interesting project by der8auer: Spray cooling with Novec 7000. Acceptable idle temperatures, nothing more. Just a POC.

But, spray cooling was used with the Cray X1 supercomputer. Small holes in the heatspreader sprayed directly onto the small chips, and the gas was returned.
October 13, 2025 at 6:12 PM
It's official! OpenAI and Broadcom announce strategic collaboration to deploy 10 GW of OpenAI-designed AI accelerators.

OpenAI and Broadcom have signed a term sheet to deploy racks incorporating the AI accelerators and Broadcom networking solutions.
October 13, 2025 at 2:51 PM
One of the slides that shows the potential of #PantherLake the best. 4P+8E+4LPE cores on par with 4P+4LPE (Lunar Lake) and better than 6P+8E+2LPE (Arrow Lake-H), where the allocation of those LPE cores had it’s hurdles.
October 11, 2025 at 11:26 AM
Robinson Lake reference design for embedded/robotics #PantherLake solutions. The CPU is rated for an extended temperature range of -40 °C to 105 °C. The memory chips are labeled with 4ZC42 DBFVB from Micron. #IntelTechTour
October 10, 2025 at 2:25 PM
This is a #Intel18A wafer with #PantherLake compute tiles.

I did a quick annotation (see 2nd picture attached).
October 9, 2025 at 3:43 PM
I had the opportunity to visit Intel's #Fab52 at the Ocotillo campus in Chandler, Arizona. This is where Intel manufactures its chips in #Intel18A. In this report, I attempt to convey the enormous dimensions and challenges involved. #IntelTechTour

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October 9, 2025 at 2:32 PM
A switch from #Crestmont to #Darkmont and thus a significant leap in CPU performance, but still platform-compatible and technically impressive with #Intel18A + #FoverosDirect3D. Intel provides further details on #ClearwaterForest, also known as #Xeon6+.

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October 9, 2025 at 2:32 PM
Based on todays details about #PantherLake and #ClearwaterForest, we took another look at the details of #Intel18A, #PowerVia (including Omni MIM), #RibbonFET, and #Foveros. #IntelTechTour

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October 9, 2025 at 2:32 PM