Tadashi G. Takaoka
@tgtakaoka.bsky.social
Pinned
Retro CPUs on the right will be placed on the ZIF socket on the left. The CPU boards have a serial EEPROM for ID.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
I finally managed to get hold of the MC68040FE in a QFP package that runs on 5V. Combined with the MC68150 bus size converter, it should work on my current 16-bit bus, 5V system! It's a bit disappointing that it's Freescale.
December 8, 2025 at 4:36 AM
I finally managed to get hold of the MC68040FE in a QFP package that runs on 5V. Combined with the MC68150 bus size converter, it should work on my current 16-bit bus, 5V system! It's a bit disappointing that it's Freescale.
The Z180 is done. The bus speed is just over 2MHz.
Plugging and unplugging it from a PLCC socket can easily damage the pins. I'm also in the process of ordering the QFP Z80180FSC and the original HD64180SH, so I'll do that soon.
I think the Z280 will be next, and i8095 needs to be finished.
Plugging and unplugging it from a PLCC socket can easily damage the pins. I'm also in the process of ordering the QFP Z80180FSC and the original HD64180SH, so I'll do that soon.
I think the Z280 will be next, and i8095 needs to be finished.
November 30, 2025 at 2:56 AM
The Z180 is done. The bus speed is just over 2MHz.
Plugging and unplugging it from a PLCC socket can easily damage the pins. I'm also in the process of ordering the QFP Z80180FSC and the original HD64180SH, so I'll do that soon.
I think the Z280 will be next, and i8095 needs to be finished.
Plugging and unplugging it from a PLCC socket can easily damage the pins. I'm also in the process of ordering the QFP Z80180FSC and the original HD64180SH, so I'll do that soon.
I think the Z280 will be next, and i8095 needs to be finished.
The KL5C80A12 is done. The bus speed is just over 3MHz.
I was able to run it with zero wait, so it's much faster than the Z80.
Setting it to zero wait means the READY signal doesn't work, so I had to use a little ingenuity.
Now I think I'll try the Z180 next, since it's very similar.
I was able to run it with zero wait, so it's much faster than the Z80.
Setting it to zero wait means the READY signal doesn't work, so I had to use a little ingenuity.
Now I think I'll try the Z180 next, since it's very similar.
November 22, 2025 at 8:44 AM
The KL5C80A12 is done. The bus speed is just over 3MHz.
I was able to run it with zero wait, so it's much faster than the Z80.
Setting it to zero wait means the READY signal doesn't work, so I had to use a little ingenuity.
Now I think I'll try the Z180 next, since it's very similar.
I was able to run it with zero wait, so it's much faster than the Z80.
Setting it to zero wait means the READY signal doesn't work, so I had to use a little ingenuity.
Now I think I'll try the Z180 next, since it's very similar.
I bought the trendy Alientek LT1. I hope I won't lose SMT components when they bounce off the tester probes.
October 29, 2025 at 9:10 AM
I bought the trendy Alientek LT1. I hope I won't lose SMT components when they bounce off the tester probes.
I'm playing around with the TMS370C. As usual, I'm using software to control the external clock via GPIO, but the oscillator monitoring mechanism is complaining that it's unstable and resetting the CPU. It's tuff.
October 19, 2025 at 7:49 AM
I'm playing around with the TMS370C. As usual, I'm using software to control the external clock via GPIO, but the oscillator monitoring mechanism is complaining that it's unstable and resetting the CPU. It's tuff.
TMS320C15 implemetation has done. Clock is just under 2MHz, less than half the max. 5MHz.
Because there was little bus signal, all instructions were executed by counting the cycles.
Multiplication took one clock, and division only required so called SUBC 16 times, so the Mandelbrot was quite fast.
Because there was little bus signal, all instructions were executed by counting the cycles.
Multiplication took one clock, and division only required so called SUBC 16 times, so the Mandelbrot was quite fast.
June 19, 2025 at 4:18 AM
TMS320C15 implemetation has done. Clock is just under 2MHz, less than half the max. 5MHz.
Because there was little bus signal, all instructions were executed by counting the cycles.
Multiplication took one clock, and division only required so called SUBC 16 times, so the Mandelbrot was quite fast.
Because there was little bus signal, all instructions were executed by counting the cycles.
Multiplication took one clock, and division only required so called SUBC 16 times, so the Mandelbrot was quite fast.
Retro CPUs on the right will be placed on the ZIF socket on the left. The CPU boards have a serial EEPROM for ID.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
June 4, 2025 at 4:27 AM
Retro CPUs on the right will be placed on the ZIF socket on the left. The CPU boards have a serial EEPROM for ID.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
The Cortex-M7 on the left identifies the CPU inserted and take care of the clock, memory and serial comm. The firmware is around 300kB including all assembler, disassembler, debugger.
TMS9900 implementation has done. Bus clock is about 2MHz.
Making 12V 4 phase clock was crucial.
Making 12V 4 phase clock was crucial.
June 2, 2025 at 7:07 AM
TMS9900 implementation has done. Bus clock is about 2MHz.
Making 12V 4 phase clock was crucial.
Making 12V 4 phase clock was crucial.
I got an i486DX4 which has 3.3V core, 5V torrerant I/O and dynamic bus sizing.
May 28, 2025 at 6:55 AM
I got an i486DX4 which has 3.3V core, 5V torrerant I/O and dynamic bus sizing.
I got two more members of Motorola 68HC family.
Considering instruction set, 68HC12 seems a younger brother of 6809, and 68HC16 is a orthodox successor of 6800.
Considering instruction set, 68HC12 seems a younger brother of 6809, and 68HC16 is a orthodox successor of 6800.
May 2, 2025 at 5:22 AM
I got two more members of Motorola 68HC family.
Considering instruction set, 68HC12 seems a younger brother of 6809, and 68HC16 is a orthodox successor of 6800.
Considering instruction set, 68HC12 seems a younger brother of 6809, and 68HC16 is a orthodox successor of 6800.
The MC68HC08AZ0 is finally complete. The bus speed is aboud 2MHz. Control signals are minimal, no NMI, aslo has instruction prefetch.I minotor every bus cycles and execute with single steps.
Thanks to 8-bit MUL and DIV, mandelbrot drawing is quite fast.
HC12 and HC16 are left to be implemented...
Thanks to 8-bit MUL and DIV, mandelbrot drawing is quite fast.
HC12 and HC16 are left to be implemented...
April 27, 2025 at 7:37 AM
The MC68HC08AZ0 is finally complete. The bus speed is aboud 2MHz. Control signals are minimal, no NMI, aslo has instruction prefetch.I minotor every bus cycles and execute with single steps.
Thanks to 8-bit MUL and DIV, mandelbrot drawing is quite fast.
HC12 and HC16 are left to be implemented...
Thanks to 8-bit MUL and DIV, mandelbrot drawing is quite fast.
HC12 and HC16 are left to be implemented...
I got most of the Motorola CPUs.
I'd like to try a CPU with built-in FPU, such as 68040 and 80486, but those require 3.3V and 32 bit data bus. CPU which can run on 16 bit data bus and 5V are up to 68030 and 80386, I think.
I'd like to try a CPU with built-in FPU, such as 68040 and 80486, but those require 3.3V and 32 bit data bus. CPU which can run on 16 bit data bus and 5V are up to 68030 and 80386, I think.
April 18, 2025 at 3:13 AM
I got most of the Motorola CPUs.
I'd like to try a CPU with built-in FPU, such as 68040 and 80486, but those require 3.3V and 32 bit data bus. CPU which can run on 16 bit data bus and 5V are up to 68030 and 80386, I think.
I'd like to try a CPU with built-in FPU, such as 68040 and 80486, but those require 3.3V and 32 bit data bus. CPU which can run on 16 bit data bus and 5V are up to 68030 and 80386, I think.
Intel is all set here too...
April 13, 2025 at 4:19 AM
Intel is all set here too...
Z80, Z180, Z280, Z380, I got everything.
I learned that Z280 and Z380 are binary incompatible while coding assembler/disassembler. They use the prefix byte, CB/DD/ED/FD, quite differently.
I learned that Z280 and Z380 are binary incompatible while coding assembler/disassembler. They use the prefix byte, CB/DD/ED/FD, quite differently.
March 31, 2025 at 12:54 AM
Z80, Z180, Z280, Z380, I got everything.
I learned that Z280 and Z380 are binary incompatible while coding assembler/disassembler. They use the prefix byte, CB/DD/ED/FD, quite differently.
I learned that Z280 and Z380 are binary incompatible while coding assembler/disassembler. They use the prefix byte, CB/DD/ED/FD, quite differently.
P8080 implementation has done. Clock is about 2MHz. VIH of Φ1 is a bit lower though.
Use RESET to resume from HALT break point. PC is observable on the bus, INTE pin exists, other registers are preserved.
Mandelbrot speed is faster than I expected, probably due to inter-register operation.
Use RESET to resume from HALT break point. PC is observable on the bus, INTE pin exists, other registers are preserved.
Mandelbrot speed is faster than I expected, probably due to inter-register operation.
March 7, 2025 at 7:14 AM
P8080 implementation has done. Clock is about 2MHz. VIH of Φ1 is a bit lower though.
Use RESET to resume from HALT break point. PC is observable on the bus, INTE pin exists, other registers are preserved.
Mandelbrot speed is faster than I expected, probably due to inter-register operation.
Use RESET to resume from HALT break point. PC is observable on the bus, INTE pin exists, other registers are preserved.
Mandelbrot speed is faster than I expected, probably due to inter-register operation.
HD6120, another PDP8, implemetation has done. Clock is about 5MHz.
HD6120 has the improved bus design, and it needs no dummy read as IM6100 does. That is a one of reasons why HD6120 is faster than IM6100.
(asciinema.org/a/705921)
HD6120 has the improved bus design, and it needs no dummy read as IM6100 does. That is a one of reasons why HD6120 is faster than IM6100.
(asciinema.org/a/705921)
March 1, 2025 at 5:50 AM
HD6120, another PDP8, implemetation has done. Clock is about 5MHz.
HD6120 has the improved bus design, and it needs no dummy read as IM6100 does. That is a one of reasons why HD6120 is faster than IM6100.
(asciinema.org/a/705921)
HD6120 has the improved bus design, and it needs no dummy read as IM6100 does. That is a one of reasons why HD6120 is faster than IM6100.
(asciinema.org/a/705921)
It look like I could ganerate an Intel 8080 clock. I can find the 8224 driver spec. but the input volatage is the only thing I can know about 8080 clock spec.
Passive level conversion can't make a pulse sharp. SYNC pulsing, so I guess it's OK.
I should strengthen the buffer and lower the pullup.
Passive level conversion can't make a pulse sharp. SYNC pulsing, so I guess it's OK.
I should strengthen the buffer and lower the pullup.
February 25, 2025 at 3:13 AM
It look like I could ganerate an Intel 8080 clock. I can find the 8224 driver spec. but the input volatage is the only thing I can know about 8080 clock spec.
Passive level conversion can't make a pulse sharp. SYNC pulsing, so I guess it's OK.
I should strengthen the buffer and lower the pullup.
Passive level conversion can't make a pulse sharp. SYNC pulsing, so I guess it's OK.
I should strengthen the buffer and lower the pullup.
Macrostore for TMS99105 has been implemented.
By injecting TMS99110 Macrostore ROM image, it can run floating point version of Mandelbrot drawing successfully.
I've been wanting to do this since I read the datasheet.
By injecting TMS99110 Macrostore ROM image, it can run floating point version of Mandelbrot drawing successfully.
I've been wanting to do this since I read the datasheet.
February 14, 2025 at 1:20 PM
Macrostore for TMS99105 has been implemented.
By injecting TMS99110 Macrostore ROM image, it can run floating point version of Mandelbrot drawing successfully.
I've been wanting to do this since I read the datasheet.
By injecting TMS99110 Macrostore ROM image, it can run floating point version of Mandelbrot drawing successfully.
I've been wanting to do this since I read the datasheet.
IM6100, one chip PDP8, implementation has done. Clock is about 5MHz. The short duration of valid address makes clock tuning hard.
Hardware implementation friendly architecture makes programming like a puzzle. Even IOT instruction clobbers AC.
(asciinema.org/a/703143)
Hardware implementation friendly architecture makes programming like a puzzle. Even IOT instruction clobbers AC.
(asciinema.org/a/703143)
February 13, 2025 at 5:05 AM
IM6100, one chip PDP8, implementation has done. Clock is about 5MHz. The short duration of valid address makes clock tuning hard.
Hardware implementation friendly architecture makes programming like a puzzle. Even IOT instruction clobbers AC.
(asciinema.org/a/703143)
Hardware implementation friendly architecture makes programming like a puzzle. Even IOT instruction clobbers AC.
(asciinema.org/a/703143)
Succeeded in converting5V to -5V and +12V using DCDC converter prototype. Logic analayzer is saturated at 10V though.
Intel 8080 could be my next target....
Intel 8080 could be my next target....
February 9, 2025 at 8:23 AM
Succeeded in converting5V to -5V and +12V using DCDC converter prototype. Logic analayzer is saturated at 10V though.
Intel 8080 could be my next target....
Intel 8080 could be my next target....
MN1613 implementation has done. Clock is about 10MHz. The info about reset sequence by pioneers helped a lot.
Mandelbrot drawing is quite simple thanks to floating point instructions (asciinema.org/a/702189)
Mandelbrot drawing is quite simple thanks to floating point instructions (asciinema.org/a/702189)
February 8, 2025 at 2:57 AM
MN1613 implementation has done. Clock is about 10MHz. The info about reset sequence by pioneers helped a lot.
Mandelbrot drawing is quite simple thanks to floating point instructions (asciinema.org/a/702189)
Mandelbrot drawing is quite simple thanks to floating point instructions (asciinema.org/a/702189)
Bionic implementation TMS99105 has also done. TMS99105 can run at maximum 24MHz, but ~4MHz is the limit of hand made clock by Cortex-M7.
The 16-bit data bus width seems quite effective. The speed of Mandelbrot drawing is explosively fast!
The 16-bit data bus width seems quite effective. The speed of Mandelbrot drawing is explosively fast!
January 12, 2025 at 9:12 AM
Bionic implementation TMS99105 has also done. TMS99105 can run at maximum 24MHz, but ~4MHz is the limit of hand made clock by Cortex-M7.
The 16-bit data bus width seems quite effective. The speed of Mandelbrot drawing is explosively fast!
The 16-bit data bus width seems quite effective. The speed of Mandelbrot drawing is explosively fast!
Bionic implementation of TMS9995 has also done. Clock freq. is ~6MHz.
TMS9995 has optimized bus cycle design, signed multiply and divde instructions, 16-bit wide access to internal RAM. The speed of Mandelbrot drawing is much faster than TMS9981.
TMS9995 has optimized bus cycle design, signed multiply and divde instructions, 16-bit wide access to internal RAM. The speed of Mandelbrot drawing is much faster than TMS9981.
January 12, 2025 at 8:21 AM
Bionic implementation of TMS9995 has also done. Clock freq. is ~6MHz.
TMS9995 has optimized bus cycle design, signed multiply and divde instructions, 16-bit wide access to internal RAM. The speed of Mandelbrot drawing is much faster than TMS9981.
TMS9995 has optimized bus cycle design, signed multiply and divde instructions, 16-bit wide access to internal RAM. The speed of Mandelbrot drawing is much faster than TMS9981.
Bionic implementation of TMS9981 has done. Clock freq. is ~7MHz.
Too many bus cycles are observed unexpectedly because registers are in main memory and 8-bit bus width. The speed of Mandelbot seems rather fast thanks to MPY and DIV instructions.
#TMS9900
Too many bus cycles are observed unexpectedly because registers are in main memory and 8-bit bus width. The speed of Mandelbot seems rather fast thanks to MPY and DIV instructions.
#TMS9900
January 10, 2025 at 4:48 AM
Bionic implementation of TMS9981 has done. Clock freq. is ~7MHz.
Too many bus cycles are observed unexpectedly because registers are in main memory and 8-bit bus width. The speed of Mandelbot seems rather fast thanks to MPY and DIV instructions.
#TMS9900
Too many bus cycles are observed unexpectedly because registers are in main memory and 8-bit bus width. The speed of Mandelbot seems rather fast thanks to MPY and DIV instructions.
#TMS9900
I'm working with TMS99105. My chip refuses BLSK instruction as ILLOP. BIND instruction works fine though.
Am I doing something wrong?
Am I doing something wrong?
January 2, 2025 at 4:48 AM
I'm working with TMS99105. My chip refuses BLSK instruction as ILLOP. BIND instruction works fine though.
Am I doing something wrong?
Am I doing something wrong?