IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a...

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Workshop presented at DVCon U.S. 2025 As the IEEE 1800.2 UVM standard continues to evolve, Accellera's release of the latest reference implementation (2020.3.1) introduces significant enhancements for verification engineers. This workshop focuses on the practical aspects of adopting the new version, providing an overview of its performance and functional improvements, as well as guidance for a smooth transition. We examine the migration process from UVM 1.2, emphasizing how the challenges faced in earlier transitions have been addressed. Particular attention is given to backward compatibility and resources now available, such as the public GitHub repository, which supports faster delivery of bug fixes and migration aids. Viewers will also gain an understanding of the performance benefits introduced and how these enhancements can accelerate verification workflows compared to legacy versions. The workshop also provides an overview of functional improvements, including enhancements that reduce the need to maintain modified versions of the UVM library. Finally, we discuss potential future enhancements, including plans for reworking the Register Abstraction Layer (RAL). Presented by: Justin Refice, NVIDIA https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

In AI it is easy to be distracted by hype and miss the real advances in technology and adoption that are making a difference today. Accellera hosted a panel at DAC on just this topic, moderated by Dan...

In this exclusive interview, Sanjay Gangal of Sanjay Tech Cafe speaks with Lu Dai, Chair of Accellera, about the organization’s pivotal role in shaping the front-end EDA standards landscape. Lu provides a deep dive into Accellera’s mission, widely adopted standards like SystemC, UVM, and UPF, and the organization’s expanding focus on AI’s impact in design and verification. Lu also highlights Accellera’s presence at DAC 2025, including the highly anticipated AI-focused luncheon panel featuring leaders from Cadence, AMD, Siemens, Synopsys, Microsoft, and NVIDIA. He previews the special engineering session on CDC and RDC standards, discusses the open and collaborative development approach, and invites viewers to engage, contribute feedback, and access resources such as IEEE 1801 and training videos via accellera.org. If you're involved in EDA, chip design, or system verification, this is a must-watch conversation on how standards are evolving to keep pace with AI and industry innovation. 👉 Don’t forget to like, comment, and subscribe for more in-depth industry interviews!

Workshop presented at DVCon U.S. 2025 Full title: Introduction of IEEE 1801-2024 (UPF 4.0) -- Improvements for the Specification and Verification of Low-Power Intent As advanced low-power architectures have become more pervasive in the industry, the complexity of these architectures has driven new methodologies for the verification, implementation, and reuse of power intent specifications. Modern low-power designs place requirements that span from enabling more flexible IP design reuse to providing well defined interfaces between analog and digital components in simulation. The IEEE 1801-2024 (UPF 4.0) standard provides several key enhancements that are required to keep pace with these innovations in low-power design. The workshop provides an overview of the enhancements to the standard from both a conceptual and a command level. New concepts such as virtual supply nets, refinable macros, and UPF libraries are introduced, as well as rearchitected features with respect to interfacing between analog and digital simulation and advanced state retention modeling. While the new IEEE 1801-2024 standard provides numerous detailed clarifications and enhancements to the previous version, this workshop focuses on the key changes that will impact most designers and changes that enable new functionality. In the six years since IEEE 1801-2018 was introduced, there have been a number of trends in design that required additional features in the standard to support. Key among these is an increasing need for co-verification of analog and mixed-signal content. Another trend is that IP providers are providing pre-verified low-power IP to their customers, but struggle to provide a flexible IP for implementation in multiple design contexts while preserving the verification sign-off on the blocks. To address these trends, IEEE 1801-2024 provides new features such as Value Conversion Methods (VCM) and HDL tunneling that help bridge the gap between the analog and digital designs, and the concept of a refinable macro to address the IP reuse requirements. Real-world usage of the previous standard (IEEE 1801-2018) has prompted clarifications and enhancements that will have a significant impact on users of the standard. For example, the modeling of state retention has been entirely reworked to provide better modeling of the retention power intent and to more accurately define requirements on the retention control signals in each phase of state retention. The new standard also codifies some common design practices to make a clear, more consistent implementation across vendors. The new concept of virtual supplies is one such case. It removes the ambiguity that exists today when supplies are used to provide port constraints or to simplify power state definitions, but do not imply a physical supply net in implementation. This workshop introduces these new concepts and their associated commands and provides an overview of the major semantic and syntax changes introduced by IEEE 1801-2024. This understanding will help users transition to the new standard and improve the quality of advanced low-power architectures and design environments. Authors: -- John Decker, IEEE P1801 Workgroup Chair -- Daniel Cross, Cadence -- Amit Srivastava, IEEE P1801 Workgroup Vice-Chair -- Lakshmanan Balasubramanian, IEEE P1801 Workgroup Secretary -- Marcelo Glusman, Cadence -- Medaramitta Jeevan, Siemens -- Gabriel Chidolue, Siemens -- Rick Koster, Siemens -- Raguvaran Easwaran, Intel -- Paul Bailey, Nordic Semiconductor -- Progyna Khondkar, Cadence https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

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Welcome to Accellera Systems Initiative's official YouTube channel. Accellera is an independent and collaborative organization with the mission to create and advance system-level design, modeling, a...

Why the Unified Power Format is necessary for verifying leading-edge designs.

Members of the Accellera CDC (Clock Domain Crossing) Working Group share the history, accomplishments, and current status of the working group. For an extended version, see: https://www.youtube.com/watch?v=k52ED1FxyrU

The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...